Document
PD - 9.1104B
IRF7205
HEXFET® Power MOSFET
Adavanced Process Technology Ultra Low On-Resistance l P-Channel MOSFET l Surface Mount l Available in Tape & Reel l Dynamic dv/dt Rating l Fast Switching Description
l l
S S S G
1 8 7
A D D D D
2
VDSS = -30V RDS(on) = 0.070Ω ID = -4.6A
3
6
4
5
T o p View
Fourth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and dual-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques. Power dissipation of greater than 0.8W is possible in a typical PCB mount application.
S O -8
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C ID @ TA = 70°C IDM PD @TC = 25°C VGS dv/dt TJ, TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range
Max.
-4.6 -3.7 -15 2.5 0.020 ± 20 -3.0 -55 to + 150
Units
A W W/°C V V/nS °C
Thermal Resistance Ratings
Parameter
Rθ JA Maximum Junction-to-Ambient
Min.
–––
Typ.
–––
Max.
50
Units
°C/W 8/25/97
IRF7205
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
∆V(BR)DSS/∆TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(ON) VGS(th) gfs IDSS IGSS Qg Q gs Q gd t d(on) tr t d(off) tf LD LS Ciss Coss Crss
Min. -30 ––– ––– ––– -1.0 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– –––
Typ. Max. Units Conditions ––– ––– V VGS = 0V, ID = -250µA -0.024 ––– V/°C Reference to 25°C, ID = -1mA ––– 0.070 VGS = -10V, I D = -4.6A Ω ––– 0.130 VGS = -4.5V, ID = -2.0A ––– -3.0 V VDS = VGS, I D = -250µA 6.6 ––– S V DS = -15V, ID = -4.6A ––– -1.0 VDS = -24V, VGS = 0V µA ––– -5.0 VDS = -15V, VGS = 0V, TJ = 70 °C ––– -100 VGS = -20V nA ––– 100 VGS = 20V 27 40 I D = -4.6A 5.2 ––– nC VDS = -15V 7.5 ––– VGS = -10V 14 30 VDD = -15V 21 60 I D = -1.0A ns 97 150 R G = 6.0Ω 71 100 RD = 10Ω
D
2.5 4.0 870 720 220
––– nH ––– ––– ––– –––
pF
Between lead,6mm(0.25in.) from package and center of die contact VGS = 0V VDS = -10V ƒ = 1.0MHz
G
S
Source-Drain Ratings and Characteristics
IS
ISM
V SD t rr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol ––– ––– -2.5 showing the A G integral reverse ––– ––– -15 p-n junction diode. S ––– ––– -1.2 V TJ = 25°C, IS = -1.25A, VGS = 0V ––– 70 100 ns TJ = 25°C, IF = -4.6A ––– 100 180 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ISD ≤ -4.6A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS ,
TJ ≤ 150°C
Surface mounted on FR-4 board, t ≤ 10sec.
IRF7205
IRF7205
C,
12
IRF7205
V DS VGS RG RD
D.U.T.
+
VDD
-10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
td(on) tr t d(off) tf
VGS 10%
90% VDS
Fig 10b. Switching Time Waveforms
100
(Z thJA )
D = 0.50 0.20 0.10 0.05 0.02 1 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.01 0.1 1 10 100
10
Thermal Response
0.1 0.0001
0.001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
IRF7205
Current Regulator Same Type as D.U.T.
QG
50KΩ 12V .2µF .3µF
-10V
QGS VG QGD
VGS
D.U.T.
+VDS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
IRF7205
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
-
+
RG VGS • dv/dt controlled by RG • I SD controlled by Duty Factor "D" • D.U.T. - Device Under Test
+ V.