Document
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
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Z86E33/733/E34 Z86E43/743/E44
CMOS Z8® OTP MICROCONTROLLERS
FEATURES
Device Z86E33 Z86733 Z86E34 Z86E43 Z86743 Z86E44 ROM (KBytes) 4 8 16 4 8 16 RAM* (Bytes) 237 237 237 236 236 236 I/O Lines 24 24 24 32 32 32 Speed (MHz) 16 16 16 16 16 16
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Programmable Crystal Oscillator, EPROM Protect, RAM Protect, Auto Latch Disable, Permanent WDT, 32 KHz Oscillator, and EPROM /Test Mode Disable Fast Instruction Pointer: 0.6µs Two Standby Modes: STOP and HALT 24/32 Input and Output Lines Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Auto Latches Auto Power-On Reset (POR) Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive
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Note: *General-Purpose s s s
Standard Temperature (VCC = 3.5V to 5.5V)
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Extended Temperature (VCC = 4.5V to 5.5V) 28-Pin DIP/SOIC/PLCC Packages (E33/733/E34) 40-Pin DIP Package (E43/743/E44) 44-Pin PLCC/QFP Packages (E43/743/E44) Software Enabled Watch-Dog Timer (WDT)
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Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 Low-Power Consumption: 60 mW
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GENERAL DESCRIPTION
The Z86E33/733/E34/E43/743/E44 8-bit CMOS One-Time Programmable (OTP) microcontrollers are members of Zilog's Z8® single-chip microcontroller family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E33/733/E34 have 24 pins and the Z86E43/743/E44 have 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
CP97DZ83300
PRELIMINARY
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Z86E33/733/E34/E43/743/E44 CMOS Z8® OTP Microcontrollers Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
Zilog
(E43/743/E44) VCC
Output Input
GND
XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT , POR
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File Program Counter OTP
Two Analog Comparators
Port 2
Port 0
Port 1
4 I/O (Bit Programmable)
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8 Address/Data or I/O (Byte Programmable) (E43/743/E44 Only)
Address or I/O (Nibble Programmable)
Figure 1. Functional Block Diagram
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PRELIMINARY
CP97DZ83300
Zilog
Z86E33/733/E34/E4.