Document
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z89138/ Z89139 (ROMLESS)
VOICE PROCESSING CONTROLLERS
FEATURES
Device Z89138 Z89139 ROM (KB) 24 RAM* (Bytes) 256 256 I/O Lines 47 47 Voltage Range 4.5V to 5.5V 4.5V to 5.5V
s s s s s s s s s s s s s
1
Clock Speeds of 20.48 or 29.49 MHz 16-Bit Digital Signal Processor (DSP) 6K Word DSP Program ROM 512 Words On-Chip DSP RAM 8-Bit A/D Converter with up to 16 kHz Sample Rate 10-Bit PWM D/A Converter Six Vectored, Prioritized Z8 Interrupts Three Vectored, Prioritized DSP Interrupts Two DSP Timers to Support Different A/D and D/A Sampling Rates IBM® PC-Based Development Tools Developer’s Toolbox for T.A.M. Applications
Note: *General-Purpose s s s
Watch-Dog Timer and Power-On Reset Improved Low-Power STOP Mode On-Chip Oscillator that Accepts a Crystal or External Clock Drive Improved Global Power-Down Mode
s
Low-Power Consumption - 200 mW (typical) Two Comparators RAM and ROM Protect On-Board Oscillator for 32.768 kHz Real-Time Clock
s s
IBM is a registered trademark of IBM Corporation.
GENERAL DESCRIPTION
The Z89138/Z89139 is a fully integrated, dual processor controller designed for voice processing applications. The I/O control processor is a Z8® MCU with 24 KB of program memory, two 8-bit counter/timers, and up to 47 I/O pins. The DSP is a 16-bit processor with a 24-bit ALU and accumulator, 512x16 bits of RAM, single cycle instructions, and 6K words of program ROM. The chip also contains a halfflash 8-bit A/D converter with up to a 16 kHz sample rate and a 10-bit PWM D/A converter. The sampling rates for the converters are programmable. The precision of the 8bit A/D can be extended by resampling the data at a lower rate in software. The Z8 and DSP processors are coupled by mailbox registers and an interrupt system. DSP or Z8 programs can be directed by events in each other’s domain. The Z89139 is the ROMless version of the Z89138. However, the on-chip DSP is not ROMless. Notes: All Signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only).
DS97TAD0201
PRELIMINARY
1
Z89138/Z89139 Voice Processing Controllers
Zilog
GENERAL DESCRIPTION (Continued)
Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
DSP Coprocessor
The DSP coprocessor is a second generation, 16-bit two’s- complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains two on-chip data RAM blocks of 256 words, a 6K word program ROM, 24-bit ALU, 16x16 multiplier, 24-bit Accumulator, shifter, six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of four pointers which can be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to .