X84256 EEPROM Datasheet

X84256 Datasheet, PDF, Equivalent


Part Number

X84256

Description

UPort Saver EEPROM

Manufacture

Xicor

Total Page 15 Pages
Datasheet
Download X84256 Datasheet


X84256
Preliminary
256K
X84256
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 3mA
• Byte or Page Write Capable
—64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Packages Options
—8, 16-Lead SOIC Packages
—14-Lead TSSOP Packages
—8-Lead XBGA Packages
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
32K x 8
Y DECODE
DATA REGISTER
©Xicor, Inc. 1998 Patents Pending
4005 1 8/24/99 WW
1 Characteristics subject to change without notice

X84256
X84256
Preliminary
PIN CONFIGURATIONS
Drawings are to the same scale, actual package sizes are
shown in inches:
CE
I/O
WP
VSS
8-LEAD SOIC
18
27
36
45
VCC
NC
OE
WE
CE
I/O
NC
NC
NC
WP
VSS
14-LEAD TSSOP
1 14
2 13
3 12
4 11
5 10
69
78
V CC
NC
NC
NC
NC
OE
WE
VCC
NC
WE
OE
8-LEAD XBGA
18
2 X84256 7
36
45
I/O
CE
VSS
WP
16-LEAD SOIC
CE
I/O
NC
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
NC
NC
NC
NC
NC
OE
WE
PIN NAMES
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes to
the device are disabled. When WP is HIGH, all functions,
including nonvolatile writes, operate normally. If a nonvol-
atile write cycle is in progress, WP going LOW will have
no effect on the cycle already underway, but will inhibit
any additional nonvolatile write cycles.
DEVICE OPERATION
The X84256 serial EEPROM is designed to interface
directly with most microprocessor buses. Standard CE,
OE, and WE signals control the read and write opera-
tions, and a single l/O line is used to send and receive
data and commands serially.
2


Features Preliminary 256K X84256 µPort Saver EE PROM DESCRIPTION MPS™ EEPROM FEATUR ES • Up to 10MHz data transfer rate 25ns Read Access Time • Direct Int erface to Microprocessors and Microcont rollers —Eliminates I/O port requirem ents —No interface glue logic require d —Eliminates need for parallel to se rial converters • Low Power CMOS —2 .5V–5.5V and 5V ±10% Versions —Sta ndby Current Less than 1µA —Active C urrent Less than 3mA • Byte or Page W rite Capable —64-Byte Page Write Mode • Typical Nonvolatile Write Cycle Ti me: 2ms • High Reliability —1,000,0 00 Endurance Cycles —Guaranteed Data Retention: 100 Years • Small Packages Options —8, 16-Lead SOIC Packages 14-Lead TSSOP Packages —8-Lead XBGA Packages The µPort Saver memories nee d no serial ports or special hardware a nd connect to the processor memory bus. Replacing bytewide data memory, the µ Port Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µPo.
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