E2 Micro-Peripheral. X88C64 Datasheet

X88C64 Datasheet PDF, Equivalent


Part Number

X88C64

Description

E2 Micro-Peripheral

Manufacture

Xicor

Total Page 14 Pages
PDF Download
Download X88C64 Datasheet


X88C64 Datasheet
APPLICATION NOTE
AVA I L A B L E
AN63
8X08581CM64icrocontroller Family Compatible
SLIC
64K
X88C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
—Isolates Read/Write Functions
Between Planes
—Allows Continuous Execution of Code
From One Plane While Writing in
the Other Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8051 Family
High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit Polling
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 100,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X88C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Tech-
nology. The X88C64 features a Multiplexed Address
and Data bus allowing a direct interface to a variety of
popular single-chip microcontrollers operating in ex-
panded multiplexed mode without the need for addi-
tional interface circuitry.
The X88C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an
auxiliary memory device for code storage.
To write to the X88C64, a three-byte command
sequence must precede the byte(s) being written. The
X88C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device
or selected 1K blocks. There are eight 1K x 8 blocks
that can be write protected individually in any combi-
nation required by the user. Block Protect, in addition
to Write Control input, allows the different segments
of the memory to have varying degrees of alterability
in normal system operation.
FUNCTIONAL DIAGRAM
CE
WR
RD
PSEN
A8–A11
ALE
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3867-1.5 7/9/96 T0/C2/D0 NS
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3867 FHD F02
1 Characteristics subject to change without notice

X88C64 Datasheet
X88C64
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The Ad-
dresses flow into the device while ALE is HIGH. After
ALE transitions from a HIGH to LOW the addresses
are latched. Once the addresses are latched these
pins input data or output data depending on RD, WR,
PSEN, and CE.
Addresses (A8–A12)
High order addresses flow into the device when ALE
is HIGH and are latched when ALE goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH and ALE is
LOW, the X88C64 is placed in the low power standby
mode.
Program Store Enable (PSEN)
When the X88C64 is to be used in a 8051 based
system, PSEN is tied directly to the microcontroller’s
PSEN output.
Read (RD)
When the X88C64 is to be used in a 8051 based
system, RD is tied directly to the microcontroller’s RD
output.
Write (WR)
When the X88C64 is to be used in a 8051 based
system, WR is tied directly to the microcontroller’s
WR output.
Address Latch Enable (ALE)
Addresses flow through the latches to address de-
coders when ALE is HIGH and are latched when ALE
transitions from a HIGH to LOW.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input
is useful in applications in which a power failure or
processor RESET could interrupt a page load cycle.
In this case, the microcontroller might drive all signals
HIGH, causing bad data to be latched into the
E2PROM. If the Write Control input is driven HIGH
(before tBLC Max) after Write (WR) goes HIGH, the
write cycle will be aborted.
When WC is LOW (tied to VSS) the X88C64 will be
enabled to perform write operations. When WC is
HIGH normal read operations may be performed, but
all attempts to write to the device will be disabled.
PIN CONFIGURATION
NC
A12
NC
NC
WC
PSEN
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
DIP/SOIC
1 24
2 23
3 22
4 21
5 20
6 19
X88C64
7 18
8 17
9 16
10 15
11 14
12 13
VCC
WR
ALE
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
3867 FHD F01
PIN NAMES
Symbol
ALE
A/D0–A/D7
A8–A12
RD
WR
PSEN
CE
WC
VSS
VCC
NC
Description
Address Latch Enable
Address Inputs/Data I/O
Address Inputs
Read Input
Write Input
Program Store Enable Input
Chip Enable
Write Control
Ground
Supply Voltage
No Connect
3867 PGM T01.1
2


Features Datasheet pdf APPLICATION NOTE A V A I L A B L E AN63 X88C64 8051 Microcontroller Family Com patible SLIC 64K X88C64 E2 Micro-Peri pheral DESCRIPTION 8192 x 8 Bit FEATU RES • • • • • • • • CONCURRENT READ WRITE™ —Dual Plane Architecture —Isolates Read/Write Fu nctions Between Planes —Allows Contin uous Execution of Code From One Plane W hile Writing in the Other Plane Multipl exed Address/Data Bus —Direct Interfa ce to Popular 8051 Family High Performa nce CMOS —Fast Access Time, 120ns — Low Power —60mA Active Maximum —500 µA Standby Maximum Software Data Prote ction Block Protect Register —Individ ually Set Write Lock Out in 1K Blocks T oggle Bit Polling —Early End of Write Detection Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle High Reliability —Endurance: 1 00,000 Write Cycle —Data Retention: 1 00 Years The X88C64 is an 8K x 8 E2PRO M fabricated with advanced CMOS Texture d Poly Floating Gate Technology. The X88C64 features a Multiplexed Address and Data bus allowing a direct in.
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