X88C75 Memory Datasheet

X88C75 Datasheet, PDF, Equivalent


Part Number

X88C75

Description

Port Expander and E2 Memory

Manufacture

Xicor

Total Page 27 Pages
Datasheet
Download X88C75 Datasheet


X88C75
APPLICATION NOTES
AVA I L A B L E
X88C75ASN6L2 •ICAN®64E• A2N66
SLIC X88C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between Planes
• Allows Continuous Execution Of Code From
One Plane While Writing In The Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 80C51 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X88C75 SLIC is a highly integrated peripheral for
the 80C51 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
two bidirectional 8-bit ports, 16 general purpose regis-
ters, programmable internal address decoding and a
multiplexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-bytes
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
PIN CONFIGURATIONS
DIP
RESET
A12
WC
PSEN
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
X88C75
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2887-2.5 4/11/97 T0/C0/D1 SH
VCC
WR
ALE
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
RD
A10
CE
A/D7
A/D6
A/D5
28288787ILILLLF0F101
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X88C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2887 ILL F02.4
Concurrent Read During Write, Block Lock, and
SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice

X88C75
X88C75 SLIC® E2
which allows Individual blocks of the memory to be
configured as read-only or read/write.
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X88C75 is accomplished through the
multiplexed address/data bus of the 80C51 type control-
lers. An internal programmable address decoder maps
the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X88C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X88C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 80C51 microcontroller. The
reading of data from the chip is controlled either by the
PSEN or the RD signal, which essentially maps the
X88C75 into both the Program and the Data Memory
address map.
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
ALE latches the address to be written into the X88C75.
The rising edge of WR latches the data to be written.
The nonvolatile memory of the X88C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X88C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X88C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock Protect, which allows the nonvolatile memory array
to be treated as 8 independent sections of 1K-bytes.
Each of these sections can be independently enabled
for write operations. This allows segmentation of the
memory contents into writable and non-writable sec-
tions, thereby, allowing certain sections of the device to
be secured so that updates can only occur in a controlled
environment. (e.g. in an automotive application, only at
FUNCTIONAL DIAGRAM
A0–A15
ADDRESS
LATCH
I/O0–I/O7
I/O
BUFFER
&
LATCH
CE
WR
RD
ALE
PSEN
WC
RESET
IRQ
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
DATA I/O BUS
RIGHT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
16 X 8
GENERAL
PURPOSE
REGISTERS
PORT SELECT
PORT
A
PORT
B
SDP
DECODE
MEM. MAP
CONFIG
REGISTER
PORT
SPECIAL
FUNCTION
REGISTERS
2887 ILL F03
2


Features APPLICATION NOTES A V A I L A B L E • AN64 ® • AN66 X88C75AN62 SLIC E2 SL IC X88C75 SLIC® E2 Microperipheral Po rt Expander and E2 Memory • High Perf ormance CMOS —Fast Access Time, 120ns —Low Power • 60mA Active • 100µ A Standby • PDIP, PLCC, and TQFP Pack aging Available DESCRIPTION The X88C75 SLIC is a highly integrated peripheral for the 80C51 family of microcontroller s. The device integrates 8K-bytes of 5V byte-alterable nonvolatile memory, two bidirectional 8-bit ports, 16 general purpose registers, programmable interna l address decoding and a multiplexed ad dress and data bus. The 5V byte-alterab le nonvolatile memory can be used as pr ogram storage, data storage, or a combi nation of both. The memory array is sep arated into two 4K-bytes sections which allows read accesses to one section wh ile a write operation is taking place i n the other section. The nonvolatile me mory also features Software Data Protec tion to protect the contents during power transitions, and an advanced Block Prote.
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