X9250 XDCP Datasheet

X9250 Datasheet, PDF, Equivalent


Part Number

X9250

Description

Quad Digitally Controlled Potentiometers (XDCP)

Manufacture

Xicor

Total Page 21 Pages
Datasheet
Download X9250 Datasheet


X9250
APPLICATION NOTE
AVAILABLE
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus/256 Taps
X9250
Quad Digitally Controlled Potentiometers (XDCP)
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot–0.4% resolution
• SPI serial interface
• Wiper resistance, 40typical @ VCC = 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100K, 50Ktotal pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
• 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
• Dual supply version of X9251
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to
the wiper terminal through switches. The position of
the wiper on the array is controlled by the user through
the SPI bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VW3/RW3
VH3/RH3
VL3/RH3
REV 1.1.5 1/31/03
www.xicor.com
Characteristics subject to change without notice. 1 of 21

X9250
X9250
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A0A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
VH/RH (VH0/RH0–VH3/RH3), VL/RL (VL0/RL0–VL3/RL3)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
VW/RW (VW0/RW0–VW3/RW3)
The wiper pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
S0
A0
VW3/RW3
VH3/RH3
VL3/RL3
V+
VCC
VL0/RL0
VH0/RH0
VW0/RW0
CS
WP
SOIC/TSSOP
1 24
2 23
3 22
4 21
5 20
6 19
X9250
7 18
8 17
9 16
10 15
11 14
12 13
HOLD
SCK
VL2/RL2
VH2/RL2
VW2/RW2
V–
VSS
VW1/RW1
VH1/RH1
VL1/RL1
A1
SI
CSP
12 3 4
A RW0 CS A1 RL1
RL0 WP SI RW1
B
VCC RH0 RH1 VSS
C
V+ RH3 RH2 V-
D
RL3 SO HOLD RW2
E
RW3 A0 SCK RL2
F
Top View–Bumps Down
REV 1.1.5 1/31/03
www.xicor.com
Characteristics subject to change without notice. 2 of 21


Features APPLICATION NOTE A V A I L A B L E AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135 Low Noise/Low Pow er/SPI Bus/256 Taps X9250 Quad Digital ly Controlled Potentiometers (XDCP™) FEATURES • • • • • • • Four potentiometers in one package 25 6 resistor taps/pot–0.4% resolution S PI serial interface Wiper resistance, 4 0Ω typical @ VCC = 5V Four nonvolatil e data registers for each pot Nonvolati le storage of wiper position Standby cu rrent < 5µA max (total package) Power supplies —VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V 1 00KΩ, 50KΩ total pot resistance Hig h reliability —Endurance – 100,000 data changes per bit per register —Re gister data retention – 100 years 24- lead SOIC, 24-lead TSSOP, 24-lead CSP ( Chip Scale Package) Dual supply version of X9251 DESCRIPTION The X9250 integra tes 4 digitally controlled potentiomete rs (XDCP) on a monolithic CMOS integrat ed circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Betw.
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