X930A MICROCONTROLLER Datasheet

X930A Datasheet, PDF, Equivalent


Part Number

X930A

Description

UNIVERSAL SERIAL BUS MICROCONTROLLER

Manufacture

Intel Corporation

Total Page 30 Pages
Datasheet
Download X930A Datasheet


X930A
ADVANCE INFORMATION
8x930Ax
UNIVERSAL SERIAL BUS
MICROCONTROLLER
s Complete Universal Serial Bus
Specification 1.0 Compatibility
— Supports Isochronous and
Non-isochronous Data
— Bidirectional Half-duplex Link
s On-chip USB Transceiver
s Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
— NRZI Encoding/Decoding and
Bit-stuffing
s USB Reset Interrupt
s Four Transmit FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Four Receive FIFOs
— Three 16-byte FIFOs
— One Configurable FIFO (up to
1 Kbyte)
s Automatic Transmit/Receive FIFO
Management
s Suspend/Resume Operation
s Three New USB Interrupt Vectors
— USB Function Interrupt
— Start of Frame
— Suspend/Resume
s Phase-locked Loop
— 12 Mbps or 1.5 Mbps Data Rate
s Low Clock Mode
s User-selectable Configurations
— External Wait State
— Address Range
— Page Mode
s Real-time Wait Function
s 256-Kbyte External Code/Data Memory
Space
s On-chip ROM Options
— 0, 8, or 16 Kbytes
s 1 Kbyte On-chip Data RAM
s Four Input/Output Ports
— 1 Open-drain port
— 3 Quasi-bidirectional Ports
s Programmable Counter Array (PCA)
— 5 Capture/Compare Modules
s Serial I/O Port (UART)
s Hardware Watchdog Timer
s Three Flexible 16-bit Timer/Counters
s Power-saving Idle and Powerdown
Modes
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Doublewords
s Code Compatible with MCS 51 and MCS
251 Microcontrollers
s 6 or 12 MHz Crystal Operation
The 8x930Ax USB microcontroller is based on an 8xC251Sx microcontroller core. It consists of standard
8xC251Sx peripherals plus an added USB function. The 8x930Ax uses the standard instruction set of the
MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function
integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and
transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume
modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification.
COPYRIGHT © INTEL CORPORATION, 1997
February 1997
Order Number: 272917-003

X930A
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The product may contain design defects or errors known as errata. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1997


Features ADVANCE INFORMATION 8x930Ax UNIVERSAL S ERIAL BUS MICROCONTROLLER s Complete Un iversal Serial Bus Specification 1.0 Co mpatibility — Supports Isochronous an d Non-isochronous Data — Bidirectiona l Half-duplex Link s On-chip USB Transc eiver s Serial Bus Interface Engine (SI E) — Packet Decoding/Generation — C RC Generation and Checking — NRZI Enc oding/Decoding and Bit-stuffing s USB R eset Interrupt s Four Transmit FIFOs Three 16-byte FIFOs — One Configura ble FIFO (up to 1 Kbyte) s Four Receive FIFOs — Three 16-byte FIFOs — One Configurable FIFO (up to 1 Kbyte) s Aut omatic Transmit/Receive FIFO Management s Suspend/Resume Operation s Three New USB Interrupt Vectors — USB Function Interrupt — Start of Frame — Suspe nd/Resume s Phase-locked Loop — 12 Mb ps or 1.5 Mbps Data Rate s Low Clock Mo de s User-selectable Configurations — External Wait State — Address Range — Page Mode s Real-time Wait Function s 256-Kbyte External Code/Data Memory Space s On-chip ROM Options — 0, 8, or 16 Kbytes s 1 Kby.
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