XC95144XL

0 R XC95144XL High Performance CPLD DS056 (v2.0) April 3, 2007 00 Features 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-CSP (117 user I/O pins) - Pb-free available for all packages Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin with local inversion - Input hysteresis on all ...