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XCR3064XL-7PC44C Dataheets PDF



Part Number XCR3064XL-7PC44C
Manufacturers Xilinx
Logo Xilinx
Description XCR3064XL 64 Macrocell CPLD
Datasheet XCR3064XL-7PC44C DatasheetXCR3064XL-7PC44C Datasheet (PDF)

0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.6) January 8, 2002 Product Specification Features • • • • • Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with.

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0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.6) January 8, 2002 Product Specification Features • • • • • Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per function block Excellent pin retention during design changes Full IEEE Standard 1149.1 boundary-scan (JTAG) Four global clocks Eight product term control terms per function block Description The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. TotalCMOS Design Technique for Fast Zero Power Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four resetable up/down, 16-bit counters at 3.3V, 25 °C). 35.0 30.0 Optimized for 3.3V systems Advanced system features Input registers Typical ICC (mA) 25.0 20.0 15.0 10.0 5.0 0.0 0 20 40 60 80 100 120 140 • • • • • • Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description Frequency (MHz) DS017_01_102401 Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C) Frequency (MHz) Typical ICC (mA) 0 0 1 0.2 5 1.0 10 2.0 20 3.9 40 7.6 60 11.3 80 14.8 100 18.5 120 22.1 140 25.6 © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS017 (v1.6) January 8, 2002 Product Specification www.xilinx.com 1-800-255-7778 1 XCR3064XL 64 Macrocell CPLD R DC Electrical Characteristics Over Recommended Operating Conditions(1) Symbol VOH(2) VOL IIL IIH ICCSB .


XCR3064XL-7CS48I XCR3064XL-7PC44C XCR3064XL-7PC44I


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