XCR3128XL

0 R XCR3128XL 128 Macrocell CPLD 0 14 DS016 (v1.8) January 8, 2002 Preliminary Product Specification Features Lowest power 128 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 128 macrocells with 3,000 usable gates Available in small footprint packages - 144-pin TQFP (108 user I/O pins) - 144-ball CS BGA (108 user I/O) - 100-pin VQFP (84 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power™ (FZP) CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial temperature range Programmable slew rate control per output Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description Description The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide 3,000 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. TotalCMOS Design T...