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X24C02 Dataheets PDF



Part Number X24C02
Manufacturers Xicor
Logo Xicor
Description Serial E2PROM
Datasheet X24C02 DatasheetX24C02 Datasheet (PDF)

Preliminary X24C02 Information 2K X24C02 Serial E2PROM 256 x 8 Bit FEATURES DESCRIPTION The X24C02 is CMOS a 2048 bit serial E2PROM, internally organized 256 x 8. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available i.

  X24C02   X24C02


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Preliminary X24C02 Information 2K X24C02 Serial E2PROM 256 x 8 Bit FEATURES DESCRIPTION The X24C02 is CMOS a 2048 bit serial E2PROM, internally organized 256 x 8. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DIP, MSOP and SOIC packages. • • • • • • • • 2.7V to 5.5V Power Supply Low Power CMOS —Active Current Less Than 1 mA —Standby Current Less Than 50 µA Internally Organized 256 x 8 Self Timed Write Cycle —Typical Write Cycle Time of 5 ms 2 Wire Serial Interface —Bidirectional Data Transfer Protocol Four Byte Page Write Operation —Minimizes Total Write Time Per Byte High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years New Hardwire—Write Control Function FUNCTIONAL DIAGRAM (8) VCC (4) VSS (7) WC START CYCLE (5) SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2PROM 64 X 32 H.V. GENERATION TIMING & CONTROL (6) SCL (3) A2 (2) A1 (1) A0 LOAD INC WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK 3838 FHD F01 DATA REGISTER DOUT © Xicor, 1991 Patents Pending 3838-1.2 7/30/96 T0/C3/D1 SH 1 Characteristics subject to change without notice X24C02 PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. Address (A0, A1, A2) The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC. Write Control (WC) The Write Control input controls the ability to write to the device. When WC is LOW (tied to VSS) the X24C02 will be enabled to perform write operations. When WC is HIGH (tied to VCC) the internal high voltage circuitry will be disabled and all writes will be disabled. A0 A1 A2 VSS DIP/SOIC/MSOP PIN CONFIGURATION 1 2 3 4 X24C02 8 7 6 5 VCC WC SCL SDA 3838 FHD F02 PIN DESCRIPTIONS Symbol A0–A2 SDA SCL WC VSS VCC Description Address Inputs Serial Data Serial Clock Write Control Ground +5V 3838 PGM T01 2 X24C02 DEVICE OPERATION The X24C02 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C02 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 3838 FHD F06 3 X24C02 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C02 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. The X24C02 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C02 will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24C02 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C02 will continue to transmit data. If an acknowledge is not detected, the X24C02 will terminate furt.


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