Document
X24C04 4K
X24C04
Serial E2PROM
512 x 8 Bit
FEATURES
DESCRIPTION
The X24C04 is a CMOS 4096 bit serial E2PROM, internally organized 512 x 8. The X24C04 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24C04 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. The X24C04 utilizes Xicor’s proprietary DirectWrite™ cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
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2.7V to 5.5V Power Supply Low Power CMOS —Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA —Standby Current Less Than 50 µA Internally Organized 512 x 8 2 Wire Serial Interface —Bidirectional Data Transfer Protocol Sixteen Byte Page Write Mode —Minimizes Total Write Time Per Byte Self Timed Write Cycle —Typical Write Cycle Time of 5 ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC Packages
FUNCTIONAL DIAGRAM
(8) VCC (4) VSS (7) TEST START CYCLE START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2PROM 32 X 128 H.V. GENERATION TIMING & CONTROL
(5) SDA
(6) SCL (3) A2 (2) A1 (1) A0
LOAD
INC
WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK
3839 FHD F01
DATA REGISTER
DOUT
DirectWrite™ is a trademark of Xicor, Inc. © Xicor, 1991 Patents Pending
3839-1
1
Characteristics subject to change without notice
X24C04
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address (A0) A0 is unused by the X24C04, however, it must be tied to VSS to insure proper device operation. Address (A1, A2) The Address inputs are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If driven they must be driven to VSS or to VCC. PIN NAMES Symbol A0–A2 SDA SCL TEST VSS VCC NC Description Address Inputs Serial Data Serial Clock Hold at VSS Ground Supply Voltage No Connect
3839 PGM T01
PIN CONFIGURATION
DIP/SOIC
A0 A1 A2 VSS 1 2 3 4 X24C04 8 7 6 5 VCC TEST SCL SDA
3839 FHD F02
SOIC
NC A0 A1 NC A2 VSS NC 1 2 3 4 5 6 7 14 13 12 X24C04 11 10 9 8 NC VCC TEST NC SCL SDA NC
3839 FHD F03
2
X24C04
DEVICE OPERATION The X24C04 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data trans.