Document
Preliminary X24C16 Information
16K
X24C16
Serial E2PROM
2048 x 8 Bit
FEATURES
DESCRIPTION
The X24C16 is a CMOS 16,384 bit serial E2PROM, internally organized 2048 X 8. The X24C16 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24C16 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. The X24C16 utilizes Xicor’s proprietary Direct WriteTM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
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2.7V to 5.5V Power Supply Low Power CMOS —Active Read Current Less Than 1 mA —Active Write Current Less Than 3 mA —Standby Current Less Than 50 µA Internally Organized 2048 x 8 2 Wire Serial Interface —Bidirectional Data Transfer Protocol Sixteen Byte Page Write Mode —Minimizes Total Write Time Per Byte Self Timed Write Cycle —Typical Write Cycle Time of 5 ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC Packages
FUNCTIONAL DIAGRAM
(8) VCC (4) VSS (7) TEST START CYCLE START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2PROM 128 X 128 H.V. GENERATION TIMING & CONTROL
(5) SDA
(6) SCL (3) A2 (2) A1 (1) A0
LOAD
INC
WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK
3840 FHD F01
DATA REGISTER
DOUT
© Xicor, 1991 Patents Pending
3840-1.1 7/29/96 T1/C0/D0 SH
1
Characteristics subject to change without notice
X24C16
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address (A0, A1, A2) The A0, A1 and A2 inputs are unused by the X24C16, however, they must be tied to VSS to insure proper device operation. PIN NAMES Symbol A0–A2 SDA SCL TEST VSS VCC NC Description Address Inputs Serial Data Serial Clock Hold at VSS Ground Supply Voltage No Connect
3840 PGM T01
PIN CONFIGURATION
DIP/SOIC A0 A1 A2 VSS 1 2 3 4 X24C16 8 7 6 5 VCC TEST SCL SDA
3840 FHD F02
SOIC
NC A0 A1 NC A2 VSS NC 1 2 3 4 5 6 7 14 13 12 X24C16 11 10 9 8 NC VCC TEST NC SCL SDA NC
3840 FHD F03
2
X24C16
DEVICE OPERATION The X24C16 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C16 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C16 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
3840 FHD F06
3
X24C16
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C16 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. Figure 2. Definition of Start and Stop The X24C16 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C16 will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24C16 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C16 will continue to transmit data. If an acknowledge is not detected, the X24C16 will terminate further data transmissions. The master must then issue a stop condition to return the X24C16 to the standby power mode and place the device into a known state.
SCL
SDA START BIT STOP BIT
3840 FHD F07
Figure 3. Acknowledge Response From R.