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X24F128 Dataheets PDF



Part Number X24F128
Manufacturers Xicor
Logo Xicor
Description 2-Wire SerialFlash with Block Lock TM Protection
Datasheet X24F128 DatasheetX24F128 Datasheet (PDF)

APPLICATION NOTE A V A I L A B L E AN84 128K X24F128 2-Wire SerialFlash with Block LockTM Protection 16K x 8 Bit FEATURES • • • • • • • • • • • • Save Critical Data With Programmable Block Lock Protection —Block Lock (0, 1/4, 1/2, or all of E2PROM Array) —Software Program Protection —Programmable Hardware Program Protect In Circuit Programmable ROM Mode Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Program Current Less Than 3mA —Standby Current Less Than.

  X24F128   X24F128


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APPLICATION NOTE A V A I L A B L E AN84 128K X24F128 2-Wire SerialFlash with Block LockTM Protection 16K x 8 Bit FEATURES • • • • • • • • • • • • Save Critical Data With Programmable Block Lock Protection —Block Lock (0, 1/4, 1/2, or all of E2PROM Array) —Software Program Protection —Programmable Hardware Program Protect In Circuit Programmable ROM Mode Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Program Current Less Than 3mA —Standby Current Less Than 1µA 1.8V to 3.6V or 5V “Univolt” Read and Program Power Supply Versions 32 Word Sector Program Mode —Minimizes Total Program Time Per Word 100KHz 2-Wire Serial Interface Internally Organized 16K x 8 Bidirectional Data Transfer Protocol Self-Timed Program Cycle —Typical Program Cycle Time of 5ms High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years 8-Lead DIP 16-Lead SOIC DESCRIPTION The X24F128 is a CMOS SerialFlash Memory, internally organized 16K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S0–S2) allow up to eight devices to share a common two wire bus. A Program Protect Register at the address location FFFFh provides three program protection features: Software Program Protect, Block Lock Protect, and Hardware Program Protect. The Software Program Protect feature prevents any nonvolatile writes to the device until the PEL bit in the Program Protect Register is set. The Block Lock Protection feature allows the user to individually block protect four blocks of the array by programming two bits in the Program Protect Register. The Programmable Hardware Program Protect feature allows the user to install the device with PP tied to VCC, program the entire memory array in circuit, and then enable the hardware program protection by programming a PPEN bit in the Program Protect Register. After this, selected blocks of the array, including the Program Protect Register itself, are permanently protected from being erased. FUNCTIONAL DIAGRAM SERIALFLASH DATA AND ADDRESS (SDA) COMMAND DECODE AND CONTROL LOGIC BLOCK LOCK AND PROGRAM PROTECT CONTROL LOGIC S2 S1 S0 DEVICE SELECT LOGIC PROGRAM PROTECT REGISTER DATA REGISTER Y DECODE LOGIC SERIALFLASH ARRAY 16K x 8 4K x 8 SCL SECTOR DECODE LOGIC 4K x 8 8K x 8 PP PROGRAM VOLTAGE CONTROL 7012 ILL F01.4 ©Xicor, 1995, 1996 Patents Pending 7012-0.8 11/25/96 T1/C0/D0 SH 1 Characteristics subject to change without notice X24F128 Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels. Program Protect (PP) The Program Protect input controls the Hardware Program Protect feature. When held LOW, hardware program protection is disabled and the device can be programmed normally. When this input is held HIGH, and the PPEN bit in the Program Protect Register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the Program Protect Register itself. PIN NAMES Symbol S0, S1, S2 SDA SCL PP VSS VCC NC Description Device Select Inputs Serial Data Serial Clock Program Protect Ground Supply Voltage No Connect 7012 FRM T01 PIN CONFIGURATION 8-LEAD DIP S0 S1 S2 VSS 1 2 3 4 X24F128 8 7 6 5 VCC PP SCL SDA 16-LEAD SOIC S0 S1 NC NC NC NC S2 VSS 1 2 3 4 5 6 7 8 X24F128 16 15 14 13 12 11 10 9 VCC PP NC NC NC NC SCL SDA 7012 ILL F02.1 2 X24F128 DEVICE OPERATION The device supports a bidirectional, bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24F128 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All .


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