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X25020 Dataheets PDF



Part Number X25020
Manufacturers Xicor
Logo Xicor
Description SPI Serial E2PROM with Block LockTM Protection
Datasheet X25020 DatasheetX25020 Datasheet (PDF)

APPLICATION NOTES A V A I L A B L E X25020 2K AN9 • AN18 • AN31 • AN37 • AN40 X25020 SPI Serial E2PROM with Block LockTM Protection DESCRIPTION 256 x 8 Bit FEATURES • • • • • • • • • • • 1MHz Clock Rate SPI Modes (0,0 & 1,1) 256 X 8 Bits —4 Byte Page Mode Low Power CMOS —10µA Standby Current —3mA Active Write Current 2.7V To 5.5V Power Supply Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection —Power-Up/Power-Down protection circuitry —Wr.

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APPLICATION NOTES A V A I L A B L E X25020 2K AN9 • AN18 • AN31 • AN37 • AN40 X25020 SPI Serial E2PROM with Block LockTM Protection DESCRIPTION 256 x 8 Bit FEATURES • • • • • • • • • • • 1MHz Clock Rate SPI Modes (0,0 & 1,1) 256 X 8 Bits —4 Byte Page Mode Low Power CMOS —10µA Standby Current —3mA Active Write Current 2.7V To 5.5V Power Supply Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection —Power-Up/Power-Down protection circuitry —Write Latch —Write Protect Pin Self-Timed Write Cycle —5ms Write Cycle Time (Typical) High Reliability —Endurance: 100,000 cycles per byte —Data Retention: 100 Years —ESD protection: 2000V on all pins 8-Lead PDlP Package 8-Lead SOIC Package The X25020 is a CMOS 2048-bit serial E2PROM, internally organized as 256 x 8. The X25020 features a serial interface and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25020 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25020 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25020 disabling all write attempts, thus providing a mechanism for limiting end user capability of altering the memory. The X25020 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM STATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 16 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 16 256 BYTE ARRAY 16 X 32 16 X 32 32 32 X 32 WP WRITE CONTROL AND TIMING LOGIC 4 8 Y DECODE DATA REGISTER Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 3834-1.8 6/10/96 T3/C1/D0 NS 3834 FHD F01 Characteristics subject to change without notice 1 X25020 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25020 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25020 will be in the standby power mode. CS LOW enables the X25020, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25020 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25020. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. DIP/SOIC Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION CS SO WP VSS 1 2 3 4 X25020 8 7 6 5 VCC HOLD SCK SI 3834 FHD F02.1 PIN NAMES Symbol CS SO SI SCK WP VSS VCC HOLD Description Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input 3834 PGM T01.1 2 X25020 PRINCIPLES OF OPERATION The X25020 is a 256 x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25020 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then .


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