Document
APPLICATION NOTE
A VA I L A B L E
AN61
128K
X25128
SPI Serial E2PROM with Block LockTM Protection
DESCRIPTION
16K x 8 Bit
FEATURES
• • • • • • •
• •
• • •
2MHz Clock Rate SPI Modes (0,0 & 1,1) 16K X 8 Bits —32 Byte Page Mode Low Power CMOS —<1µ A Standby Current —<5mA Active Current 2.7V To 5.5V Power Supply Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection —Power-Up/Power-Down protection circuitry —Write Enable Latch —Write Protect Pin Self-Timed Write Cycle —5ms Write Cycle Time (Typical) High Reliability —Endurance: 100,000 cycles —Data Retention: 100 Years —ESD protection: 2000V on all pins 14-Lead SOIC Package 16-Lead SOIC Package 8-Lead PDIP Package FUNCTIONAL DIAGRAM
STATUS REGISTER WRITE PROTECT LOGIC
The X25128 is a CMOS 131,072-bit serial E2PROM, internally organized as 16K x 8. The X25128 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25128 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25128 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25128 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25128 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
X DECODE LOGIC 128
16K BYTE ARRAY
16 X 256 SO SI SCK CS HOLD 256 32 X 256 COMMAND DECODE AND CONTROL LOGIC
128
16 X 256
WP
WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER
3091 FM F01
©Xicor Inc. 1994, 1995, 1996 Patents Pending 3091-2.9 5/14/97 T2/C0/D2 SH
1
Characteristics subject to change without notice
X25128
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is high, the X25128 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25128 will be in the standby power mode. CS low enables the X25128, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25128 status register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes operate normally. WP going low while CS is still low will interrupt a write to the X25128 status register. If the internal write cycle has already been initiated, WP going low will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25128 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “0”. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought low while SCK is Low. To resume communication, HOLD is brought high, again while SCK is
.430” CS SO WP VSS 1 2 3 4 .325” X25128 .394”
low. If the pause feature is not used, HOLD should be held high at all times. PIN CONFIGURATION
Not to scale 14 Lead SOIC CS SO NC .344” NC NC WP VSS 1 2 3 4 5 6 7 .244” 16 Lead SOIC CS SO NC NC NC NC WP VSS 1 2 3 4 5 6 7 8 .244” 8 Lead PDIP 8 7 6 5 VCC HOLD SCK SI
3091 FM 02
14 13 12 X24128 11 10 9 8
VCC HOLD NC NC NC SCK SI
16 15 14 X25128 13 12 11 10 9
VCC HOLD NC NC NC NC SCK SI
PIN NAMES Symbol CS
SO SI SCK
Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect
3091 FM T01
WP
VSS VCC
HOLD
NC
2
X25128
PRINCIPLES OF OPERATION The X25128 is a 8K x 8 E PROM designed to in.