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X25138 Dataheets PDF



Part Number X25138
Manufacturers Xicor
Logo Xicor
Description 5MHz SPI Serial E2PROM with Block Lock PROTECTION
Datasheet X25138 DatasheetX25138 Datasheet (PDF)

128K X25138 16K x 8 Bit 5MHz SPI Serial E2PROM with Block LockTM Protection FEATURES DESCRIPTION The X25138 is a CMOS 128K-bit serial E2PROM, internally organized as 16K x 8. The X25138 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to sh.

  X25138   X25138


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128K X25138 16K x 8 Bit 5MHz SPI Serial E2PROM with Block LockTM Protection FEATURES DESCRIPTION The X25138 is a CMOS 128K-bit serial E2PROM, internally organized as 16K x 8. The X25138 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25138 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25138 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25138 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25138 utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. • • • • • • • • • • • 5MHz Clock Rate Low Power CMOS <1mA Standby Current <5mA Active Current 2.5V To 5.5V Power Supply SPI Modes (0,0 & 1,1) 16K X 8 Bits 32 Byte Page Mode Block Lock™ Protection Protect 1/4, 1/2 or all of E2PROM Array Programmable Hardware Write Protection In-Circuit Programmable ROM Mode Built-in Inadvertent Write Protection Power-Up/Down protection circuitry Write Enable Latch Write Protect Pin Self-Timed Write Cycle 5ms Write Cycle Time (Typical) High Reliability Endurance: 100,000 cycles Data Retention: 100 Years ESD protection: 2000V on all pins Packages 8-Lead XBGA 8, 14-Lead SOIC 8-Lead PDIP 8-Lead TSSOP FUNCTIONAL DIAGRAM ST ATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 128 128 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 128 128 X 256 16K BYTE ARRAY 256 256 X 256 WP WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc. ÓXicor, Inc. 1998 Patents Pending 7056–1.5 8/13/98 T2/C0/D1 EW 1 DATA REGISTER 7037 FRM F01 Characteristics subject to change without notice X25138 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25138 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25138 will be in the standby power mode. CS LOW enables the X25138, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25138 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the PIN NAMES Symbol CS SO SI SCK X25138 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25138 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. Hold (HOLD) HOLD is used in conjunction with the CS pin to pause the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause PIN CONFIGURATION 8-LEAD TSSOP HOLD Vcc CS SO 1 2 3 4 8 7 6 5 SCK SI Vss .114” WP X25138 .252 in. 8-Lead XBGA: Top View .078” HOLD 1 VCC 2 SI 8 S0 .238” 7 CS 6 VSS 5 WP 3 SCK 4 14 Lead SOIC CS SO NC 1 2 3 4 5 6 7 .228” X25138 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI Description Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect 7037 FRM T01 .336” NC NC WP VSS WP VSS VCC 8 Lead PDIP/SOIC CS SO WP VSS 1 2 3 4 X25138 8 7 6 5 VCC HOLD SCK SI HOLD NC 3091 FM 03 2 X25138 the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOL.


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