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X25328 Dataheets PDF



Part Number X25328
Manufacturers Xicor
Logo Xicor
Description V CC Supervisory Circuit w/Serial E 2 PROM
Datasheet X25328 DatasheetX25328 Datasheet (PDF)

64K 32K 16K FEATURES X25648/49, X25328/29, X25168/69 VCC Supervisory Circuit w/Serial E2PROM DESCRIPTION 8K x 8 Bit 4K x 8 Bit 2K x 8 Bit • Low Vcc Detection and Reset Assertion —Reset Signal Valid to Vcc=1V • Save Critical Data With Block LockTM Protection —Block LockTM Protect 0, 1/4, 1/2 or all of Serial E2PROM Memory Array • In Circuit Programmable ROM Mode • Long Battery Life With Low Power Consumption —<1µA Max Standby Current —<5mA Max Active Current during Write —<400µA Max Active Cur.

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64K 32K 16K FEATURES X25648/49, X25328/29, X25168/69 VCC Supervisory Circuit w/Serial E2PROM DESCRIPTION 8K x 8 Bit 4K x 8 Bit 2K x 8 Bit • Low Vcc Detection and Reset Assertion —Reset Signal Valid to Vcc=1V • Save Critical Data With Block LockTM Protection —Block LockTM Protect 0, 1/4, 1/2 or all of Serial E2PROM Memory Array • In Circuit Programmable ROM Mode • Long Battery Life With Low Power Consumption —<1µA Max Standby Current —<5mA Max Active Current during Write —<400µA Max Active Current during Read • 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation • 2MHz Clock Rate • Minimize Programming Time —32 Byte Page Write Mode —Self-Timed Write Cycle —5ms Write Cycle Time (Typical) • SPI Modes (0,0 & 1,1) • Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Write Enable Latch —Write Protect Pin • High Reliability • Available Packages —14-Lead SOIC (X2564X) —14-Lead TSSOP (X2532X, X2516X) —8-Lead SOIC (X2532X, X2516X) BLOCK DIAGRAM SI SO SCK CS DATA REGISTER COMMAND DECODE & CONTROL LOGIC RESET CONTROL These devices combines two popular functions, Supply Voltage Supervision and Serial E2PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The user’s system is protected from low voltage conditions by the devices low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET/RESET is asserted until Vcc returns to proper operating levels and stabilizes. The memory portion of the device is a CMOS Serial E2PROM array with Xicor’s Block LockTM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. PAGE DECODE LOGIC X - DECODE LOGIC 32 SERIAL E2PROM ARRAY 8 RESET/RESET STATUS REGISTER VCC LOW VOLTAGE SENSE WP PROGRAMMING, BLOCK LOCK & ICP ROM CONTROL HIGH VOLTAGE CONTROL 7036 FRM 01 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7032 -1.1 6/17/97 T1/C0/D0 SH 1 Characteristics subject to change without notice X25648/49, X25328/29, X25168/69 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the device is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the device Status Register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes to the Status Register operate normally. If an internal Status Register Write Cycle has already been initiated, WP going low while WPEN is a “1” will have no effect on this write. Subsequent write attempts to the Status Register under these conditions will be disabled. The WP pin function is blocked when the WPEN bit in the Status Register is “0”. This allows the user to install the device in a system with WP pin grounded and still be able to program the Status Register. The WP pin functions will be enabled when the WPEN bit is set to a “1”. Reset (RESET/RESET) RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. PIN CONFIGURATION 14-LEAD SOIC NC CS CS SO WP VSS NC 1 2 3 4 5 6 7 X25648/49 14 13 12 11 10 9 8 NC V CC V CC RESET/RESET SCK SI NC 8-LEAD SOIC CS SO WP VSS 1 8 2 X25328/29 7 X25168/69 3 6 4 5 V CC RESET/RESET SCK SI 14-LEAD TSSOP CS SO NC NC NC WP VSS 1 2 14 13 V CC RESET/RESET NC NC NC SCK SI 7036 FRM 02 3 X25328/29 12 4 X25168/69 11 5 6 7 10 9 8 PIN NAMES Symbol CS SO SI SCK WP VSS VCC RESET/RESET Description Chip Select Input Serial Output Serial Input Serial Clock Input Program Protect Input Ground Supply Voltage Reset Output 7036 FRM T01 2 X25648/49, X25328/29, X25168/69 PRINCIPLES OF OPERATIO.


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