X25642 Protection Datasheet

X25642 Datasheet, PDF, Equivalent


Part Number

X25642

Description

Advanced SPI Serial E 2 PROM with Block Lock TM Protection

Manufacture

Xicor

Total Page 16 Pages
Datasheet
Download X25642 Datasheet


X25642
APPLICATION NOTE
A V A I LABLE
AN19 • AN38 • AN41 • AN61
64K
X25642
8K x 8 Bit
Advanced SPI Serial E2PROM with Block LockTM Protection
FEATURES
2MHz Clock Rate
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Packages
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25642 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25642 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25642 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SO
SI
SCK
CS
HOLD
STATUS
REGISTER
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
64
64
128
8K BYTE
ARRAY
64 X 256
64 X 256
128 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3132-1.0 1/17/97 T5/C0/D1 SH
1
32 8
Y DECODE
DATA REGISTER
3132 ILL F01.1
Characteristics subject to change without notice

X25642
X25642
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25642 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25642 will be
in the standby power mode. CS LOW enables the
X25642, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25642 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including
nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
7037 FRM T01
X25642 status register. If the internal write cycle has
already been initiated, WP going LOW will have no
affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25642 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
SOIC/DIP
Not to Scale
CS
.197" SO
SOIC
Only
WP
VSS
18
27
X25642
36
45
VCC
HOLD
SCK
SI
.244"
SOIC
NC
CS*
CS*
.345"
SO
WP
VSS
NC
1 14
2 13
3 12
4 X25642 11
5 10
69
78
NC
NC
VCC
HOLD
SCK
SI
NC
.244"
NC
CS
NC
SO
NC
.300"
NC
WP
VSS
NC
NC
TSSOP
1 2200
2 1199
3 1188
4 1177
5 1166
6 X25642 1155
7 1144
8 1133
9 1122
10 1111
NC
VCC
NC
HOLD
NC
NC
SCK
SI
NC
NC
.252"
3132 ILL F02.5
* Pin 2 and Pin 3 are internally connected. Only one CS needs to
be connected externally.
2


Features APPLICATION NOTE A V A I LA B L E AN19 AN38 • AN41 • AN61 64K X25642 8K x 8 Bit Advanced SPI Serial E2PROM with Block LockTM Protection FEATURES DESCRIPTION The X25642 is a CMOS 65,536 -bit serial E2PROM, internally organize d as 8K x 8. The X25642 features a Seri al Peripheral Interface (SPI) and softw are protocol allowing operation on a si mple three-wire bus. The bus signals ar e a clock input (SCK) plus separate dat a in (SI) and data out (SO) lines. Acce ss to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus . The X25642 also features two addition al inputs that provide the end user wit h added flexibility. By asserting the HOLD input, the X25642 will ignore tran sitions on its inputs, thus allowing th e host to service higher priority inter rupts. The WP input can be used as a ha rdwire input to the X25642 disabling al l write attempts to the status register , thus providing a mechanism for limiting end user capability of alteri.
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