Document
64K 32K 16K
X25644/46 X25324/26 X25164/66
Programmable Watchdog Timer w/Serial E2PROM
DESCRIPTION
8K x 8 Bit 4K x 8 Bit 2K x 8 Bit
FEATURES • Programmable Watchdog Timer with Reset Assertion —Reset Signal Valid to Vcc=1V —Power Up Reset Control • Save Critical Data With Block LockTM Protection —Block LockTM Protect 0, 1/4, 1/2 or all of Serial E2PROM Memory Array • In Circuit Programmable ROM Mode • Long Battery Life With Low Power Consumption —<50µA Max Standby Current, Watchdog On —<1µA Max Standby Current, Watchdog Off —<5mA Max Active Current during Write —<400µA Max Active Current during Read • 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation • 2MHz Clock Rate • Minimize Programming Time —32 Byte Page Write Mode —Self-Timed Write Cycle —5ms Write Cycle Time (Typical) • SPI Modes (0,0 & 1,1) • Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Write Enable Latch —Write Protect Pin • High Reliability • Available Packages —14-Lead SOIC (X2564x) —14-Lead TSSOP (X2532x, X2516x) —8-Lead SOIC (X2532x, X2516x) BLOCK DIAGRAM
SI SO SCK CS RESET/RESET DATA REGISTER COMMAND DECODE & CONTROL LOGIC RESET CONTROL
These devices combine two popular functions, Watchdog Timer, and Serial E2PROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET/RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial E2PROM array with Xicor’s Block LockTM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.
PAGE DECODE LOGIC X - DECODE LOGIC 32 SERIAL E2PROM ARRAY 8
STATUS REGISTER
WATCHDOG TIMER
WP
©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7050 -1.0 6/20/97 T0/C0/D0 SH
WRITE, BLOCK LOCK & ICP ROM CONTROL 1
HIGH VOLTAGE CONTROL
7029 FRM 01 Characteristics subject to change without notice
X25644/46 X25324/26 X25164/66
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latc.