X25C02 E2PROM Datasheet

X25C02 Datasheet, PDF, Equivalent


Part Number

X25C02

Description

SPI Serial E2PROM

Manufacture

Xicor

Total Page 14 Pages
Datasheet
Download X25C02 Datasheet


X25C02
APPLICATION NOTES
AVA I L A B L E
X25C02AN9 • AN18 • AN31 • AN37 • AN40
2K
X25C02
SPI Serial E2PROM
256 x 8 Bit
FEATURES
1MHz Clock Rate
256 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—150µA Standby Current
—2mA Active Current
5V Power Supply
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Available Packages
—8-Lead MSOP
—8-Lead PDlP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E2PROM, inter-
nally organized as 256 x 8. The X25C02 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25C02 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
The X25C02 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Writeis a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3843-1.6 6/10/96 T5/C1/D1 NS
X 64
DECODE
LOGIC
256 BYTE ARRAY
(64 X 32)
48
Y DECODE
DATA REGISTER
3843 FHD F01
Characteristics subject to change without notice
1

X25C02
X25C02
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All data, opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are sampled or latched on the rising edge
of the clock input, while data on the SO pin change after
the falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25C02 is deselected and the
SO output pin is at HIGH impedance and unless an
internal write operation is underway, the X25C02 will be
PIN CONFIGURATION
CS
SO
WP
VSS
MSOP/DIP/SOIC
18
27
X25C02
36
45
VCC
HOLD
SCK
SI
3843 FHD F02.2
in the standby power mode. CS LOW enables the
X25C02, placing it in the active power mode. It should be
noted that after power-up, a HIGH to LOW transition on
CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25C02 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25C02. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
3843 PGM T01
2


Features APPLICATION NOTES A V A I L A B L E X25 C02 2K AN9 • AN18 • AN31 • AN37 • AN40 X25C02 SPI Serial E2PROM 256 x 8 Bit FEATURES DESCRIPTION The X25 C02 is a CMOS 2048-bit serial E2PROM, i nternally organized as 256 x 8. The X25 C02 features a serial interface and sof tware protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate d ata in (SI) and data out (SO) lines. Ac cess to the device is controlled throug h a chip select (CS) input, allowing an y number of devices to share the same b us. The X25C02 also features two additi onal inputs that provide the end user w ith added flexibility. By asserting the HOLD input, the X25C02 will ignore tra nsitions on its inputs, thus allowing t he host to service higher priority inte rrupts. The WP input can be used as a h ardwire input to the X25C02 disabling a ll write attempts, thus providing a mec hanism for limiting end user capability of altering the memory. The X25C02 utilizes Xicor’s proprietary Direct.
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