X28LC512 Datasheet PDF | Xicor





(PDF) X28LC512 Datasheet PDF

Part Number X28LC512
Description 3.3 Volt/ Byte Alterable E2PROM
Manufacture Xicor
Total Page 19 Pages
PDF Download Download X28LC512 Datasheet PDF

Features: X28LC512/X28LC513 512K X28LC512/X28LC51 3 3.3 Volt, Byte Alterable E2PROM 64K x 8 Bit FEATURES • • • • • • • • Low VCC Operation: V CC = 3.3V ±10% Access Time: 150ns Simp le Byte and Page Write —Self-Timed No Erase Before Write —No Complex Pr ogramming Algorithms —No Overerase Pr oblem Low Power CMOS: —Active: 25mA Standby: 150µA Software Data Protect ion —Protects Data Against System Lev el Inadvertant Writes High Speed Page W rite Capability Highly Reliable Direct Write™ Cell —Endurance: 10,000 Writ e Cycles —Data Retention: 100 Years E arly End of Write Detection —DATA Pol ling —Toggle Bit Polling Two PLCC an d LCC Pinouts —X28LC512 —X28LC010 E 2PROM Pin Compatible —X28LC513 —Com patible with Lower Density E2PROMs DES CRIPTION The X28LC512/513 is a low-powe r 64K x 8 E2PROM, fabricated with Xicor ’s proprietary, high performance, flo ating gate CMOS technology. The X28LC51 2/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS. The X28LC51.

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X28LC512 datasheet
X28LC512/X28LC513
512K
X28LC512/X28LC513
3.3 Volt, Byte Alterable E2PROM
64K x 8 Bit
FEATURES
Low VCC Operation: VCC = 3.3V ±10%
Access Time: 150ns
Simple Byte and Page Write
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 25mA
—Standby: 150µA
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write™ Cell
—Endurance: 10,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
PIN CONFIGURATIONS
Two PLCC and LCC Pinouts
—X28LC512
—X28LC010 E2PROM Pin Compatible
—X28LC513
—Compatible with Lower Density E2PROMs
DESCRIPTION
The X28LC512/513 is a low-power 64K x 8 E2PROM,
fabricated with Xicor’s proprietary, high performance,
floating gate CMOS technology. The X28LC512/513
features the JEDEC approved pinout for bytewide memo-
ries, compatible with industry standard EPROMS.
The X28LC512/513 supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less than
2.5 seconds. The X28LC512/513 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28LC512/513 supports the Soft-
ware Data Protection option.
PLCC
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLASTIC DIP
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
X28LC512
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3005 ILL F02.1
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3005-3.2 8/5/97 T2/C0/D0 EW
TSOP
X28LC512
1
40 OE
39 A10
38 CE
37 I/O7
36 I/O6
35 I/O5
34 I/O4
33 I/O3
32 NC
31 NC
30 VSS
29 NC
28 NC
27 I/O2
26 I/O1
25 I/O0
24 A0
23 A1
22 A2
21 A3
3005 ILL F22.2
30
A7
A6
5 4 3 2 32 31 29
6 1 28
A14
A13
A5 7
27 A8
A4
A3
8 26
9
X28LC512
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20 21
I/O7
3005 ILL F03
PLCC
30
A6
A5
5 4 3 2 32 31 29
6 1 28
A8
A9
A4 7
27 A11
A3
A2
8 26
9
X28LC513
(TOP VIEW)
25
NC
OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
14
15 16 17 18 19 20 21
I/O6
3005 ILL F04.1
Characteristics subject to change without notice

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