Document
X28LC512/X28LC513 512K
X28LC512/X28LC513
3.3 Volt, Byte Alterable E2PROM
64K x 8 Bit
FEATURES
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Low VCC Operation: VCC = 3.3V ±10% Access Time: 150ns Simple Byte and Page Write —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem Low Power CMOS: —Active: 25mA —Standby: 150µA Software Data Protection —Protects Data Against System Level Inadvertant Writes High Speed Page Write Capability Highly Reliable Direct Write™ Cell —Endurance: 10,000 Write Cycles —Data Retention: 100 Years Early End of Write Detection —DATA Polling —Toggle Bit Polling
Two PLCC and LCC Pinouts —X28LC512 —X28LC010 E2PROM Pin Compatible —X28LC513 —Compatible with Lower Density E2PROMs
DESCRIPTION
The X28LC512/513 is a low-power 64K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. The X28LC512/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS. The X28LC512/513 supports a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28LC512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28LC512/513 supports the Software Data Protection option.
PIN CONFIGURATIONS
PLCC
A12 A15 NC NC VCC WE NC
PLASTIC DIP NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X28LC512 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3
A11 A9 A8 A13 A14 NC NC NC WE VCC NC NC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
30 32 31 29 54 3 2 1 6 28 7 27 26 8 X28LC512 25 9 (TOP VIEW) 24 10 11 23 12 22 13 15 16 17 18 19 20 21 14
I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6
A14 A13 A8 A9 A11 OE A10 CE I/O7
X28LC512
3005 ILL F03
PLCC
A7 A12 A14 A15 VCC WE A13 A6 A5 A4 A3 A2 A1 A0 NC I/O0 30 32 31 29 54 3 2 1 6 28 7 27 26 8 X28LC513 25 9 (TOP VIEW) 24 10 11 23 12 22 13 15 16 17 18 19 20 21 14 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 3005 ILL F04.1 A8 A9 A11 NC OE A10 CE I/O7 I/O6 Characteristics subject to change without notice
3005 ILL F22.2
3005 ILL F02.1
© Xicor, Inc. 1991, 1995, 1996 Patents Pending 3005-3.2 8/5/97 T2/C0/D0 EW
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X28LC512/X28LC513
PIN DESCRIPTIONS Addresses (A0–A15) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X28LC512/513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28LC512/513. PIN NAMES Symbol A0–A15 I/O0–I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable 3.3V ± 10% Ground No Connect
3005 PGM T01
FUNCTIONAL DIAGRAM
A7–A15
X BUFFERS LATCHES AND DECODER
512K-BIT E2PROM ARRAY
A0–A6
Y BUFFERS LATCHES AND DECODER
I/O BUFFERS AND LATCHES
I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE WE VCC VSS
3005 ILL F01
CONTROL LOGIC AND TIMING
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X28LC512/X28LC513
DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28LC512/513 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X28LC512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28LC512/513 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the in.