X5045 EEPROM Datasheet

X5045 Datasheet, PDF, Equivalent


Part Number

X5045

Description

CPU Supervisor with 4K SPI EEPROM

Manufacture

Xicor

Total Page 20 Pages
Datasheet
Download X5045 Datasheet


X5045
4K
X5043/X5045
512 x 8 Bit
CPU Supervisor with 4K SPI EEPROM
FEATURES
• Selectable time out watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<10µA max standby current, watchdog off
—<2mA max active current during read
• 2.7V to 5.5V and 4.5V to 5.5V power supply
versions
• 4Kbits of EEPROM–1M write cycle endurance
• Save critical data with Block Lockmemory
—Protect 1/4, 1/2, all or none of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• 3.3MHz clock rate
• Minimize programming time
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead MSOP, 8-lead SOIC, 8-pin PDIP
—14-lead TSSOP
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscil-
lator to stabilize before the processor executes code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
1Kbits
1Kbits
2Kbits
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET/RESET
X5043 = RESET
X5045 = RESET
Power on and
VCC + Low Voltage
Reset
VTRIP
-
Generation
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 1 of 20

X5045
X5043/X5045
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
8-Lead SOIC/PDIP/MSOP
CS/WDI
SO
WP
VSS
18
27
3 X5043/45 6
45
VCC
RESET/RESET
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
14-Lead TSSOP
1 14
2 13
3 12
4 X5043/45 11
5 10
69
78
VCC
RESET/RESET
NC
NC
NC
SCK
SI
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the fall-
ing edge of the clock input.
Chip Select (CS)
When CS is high, the X5043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X5043/45 will
be in the standby power mode. CS low enables the
X5043/45, placing it in the active power mode. It should
be noted that after power-up, a high to low transition on
CS is required prior to the start of any operation.
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043/45 are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including non vol-
atile writes operate normally. WP going low while CS is
still low will interrupt a write to the X5043/45. If the
internal write cycle has already been initiated, WP
going low will have no affect on a write.
Reset (RESET, RESET)
X5043/45, RESET/RESET is an active low/HIGH,
open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if the
Watchdog timer is enabled and CS remains either high
or low longer than the Watchdog time out period. A fall-
ing edge of CS will reset the watchdog timer.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
RESET/RESET
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice. 2 of 20


Features 4K X5043/X5045 CPU Supervisor with 4K S PI EEPROM 512 x 8 Bit FEATURES • Se lectable time out watchdog timer • Lo w VCC detection and reset assertion — Five standard reset threshold voltages —Re-program low VCC reset threshold v oltage using special programming sequen ce. —Reset signal valid to VCC = 1V Long battery life with low power con sumption —<50µA max standby current, watchdog on —<10µA max standby curr ent, watchdog off —<2mA max active cu rrent during read • 2.7V to 5.5V and 4.5V to 5.5V power supply versions • 4Kbits of EEPROM–1M write cycle endur ance • Save critical data with Block Lock™ memory —Protect 1/4, 1/2, all or none of EEPROM array • Built-in i nadvertent write protection —Write en able latch —Write protect pin • 3.3 MHz clock rate • Minimize programming time —16-byte page write mode —Sel f-timed write cycle —5ms write cycle time (typical) • SPI modes (0,0 & 1,1 ) • Available packages —8-lead MSOP, 8-lead SOIC, 8-pin PDIP —14-lead TSSOP BLOCK DIAGRAM Watchdog Transition Det.
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