X5083 EEPROM Datasheet
CPU Supervisor with 8Kbit SPI EEPROM
|Total Page||21 Pages|
CPU Supervisor with 8Kbit SPI EEPROM
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock™ memory
—Block lock first or last page, any 1/4 or lower 1/2
of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
—16 byte page write mode
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
• Communications Equipment
—Routers, Hubs, Switches
—Set Top Boxes
• Industrial Systems
• Computer Systems
• Battery Powered Equipment
POR and Low
Reset & Watchdog
Standard VTRIP Level
See “Ordering Information” on page 21 for
For Custom Settings, call Xicor.
REV 1.1.6 6/25/02
Characteristics subject to change without notice. 1 of 21
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Super-
vision, and Block Lock Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC trip
point. RESET is asserted until VCC returns to the
proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to ﬁne-tune the threshold
for applications requiring higher precision.
8-Lead SOIC, PDIP
3 X5083 6
PDIP) TSSOP Name
1 3 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high
impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in the active power mode. Prior to the
start of any operation after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET
2 4 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The
falling edge of the serial clock (SCK) clocks the data out.
5 7 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data
on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes
(Table 1), addresses and data MSB ﬁrst.
6 8 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
3 5 WP Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited.
This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the
device operates normally.
4 6 VSS Ground
8 2 VCC Supply Voltage
7 1 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the
minimum VCC sense level for 250ms. RESET goes active if the watchdog timer is enabled and
CS remains either HIGH or LOW longer than the selectable watchdog time out period.
A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about
1V and remains active for 250ms after the power supply stabilizes.
REV 1.1.6 6/25/02
Characteristics subject to change without notice. 2 of 21
|Features||X5083 CPU Supervisor with 8Kbit SPI EEPR OM FEATURES • Low VCC detection and r eset assertion —Four standard reset t hreshold voltages 4.63V, 4.38V, 2.93V, 2.63V —Re-program low VCC reset thres hold voltage using special programming sequence. —Reset signal valid to VCC = 1V • Selectable time out watchdog t imer • Long battery life with low pow er consumption —<50µA max standby cu rrent, watchdog on —<1µA max standby current, watchdog off —<400µA max a ctive current during read • 8Kbits of EEPROM • Save critical data with Blo ck Lock™ memory —Block lock first o r last page, any 1/4 or lower 1/2 of EE PROM array • Built-in inadvertent wri te protection —Write enable latch — Write protect pin • SPI Interface - 3 .3MHz clock rate • Minimize programmi ng time —16 byte page write mode —5 ms write cycle time (typical) • SPI m odes (0,0 & 1,1) • Available packages —8-lead TSSOP, 8-lead SOIC, 8-Lead P DIP BLOCK DIAGRAM POR and Low Voltage Reset Generation Reset & Watchdog Timebase Watchdog Transition Detector Wa.|
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