X5645 Supervisor Datasheet

X5645 Datasheet, PDF, Equivalent


Part Number

X5645

Description

CPU Supervisor

Manufacture

Xicor

Total Page 19 Pages
Datasheet
Download X5645 Datasheet


X5645
Replaces X25643/X25645
X5643/X5645
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—8-lead PDIP, 14-lead SOIC
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
VCC
Watchdog Transition
Detector
Protect Logic
Data
Register
Command
Decode &
Control
Logic
Status
Register
16Kbits
16Kbits
VCC Threshold
Reset logic
32Kbits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power On and
Low Voltage
Reset
Generation
RESET/RESET
X5643 = RESET
X5645 = RESET
REV 1.1.1 3/5/01
www.xicor.com
Characteristics subject to change without notice. 1 of 19

X5645
X5643/X5645
PIN CONFIGURATION
CS/WDI
SO
WP
VSS
8-Lead PDIP
18
27
3 X5643/45 6
45
VCC
RESET/RESET
SCK
SI
NC
CS/WDI
CS/WDI
SO
WP
VSS
NC
14-Lead SOIC
1 14
2 13
3 12
4 X5643/45 11
5 10
69
78
NC
VCC
VCC
RESET/RESET
SCK
SI
NC
Pin
PDIP
1
2
5
6
3
4
8
7
Pin
SOIC
2&3
Pin
TSSOP
2
Name
CS/WDI
4 3 SO
9 13 SI
10 14 SCK
5 7 WP
6 8 VSS
12 & 13 19
VCC
11 18 RESET/
RESET
1, 7, 8, 1, 4–6,
14 9–12,
15–17, 20
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is
at a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, plac-
ing it in the active power mode. Prior to the start of any operation after power
up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the in-
put data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level.
It will remain active until VCC rises above the minimum VCC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET
goes active on power up at about 1V and remains active for 200ms after the
power supply stabilizes.
No internal connections
REV 1.1.1 3/5/01
www.xicor.com
Characteristics subject to change without notice. 2 of 19


Features Replaces X25643/X25645 X5643/X5645 CPU Supervisor with 64Kbit SPI EEPROM FEATU RES • Selectable watchdog timer • L ow VCC detection and reset assertion Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming seque nce —Reset signal valid to VCC = 1V Determine watchdog or low voltage re set with a volatile flag bit • Long battery life with low power consumption —<50µA max standby current, watchdo g on —<1µA max standby current, watc hdog off —<400µA max active current during read • 64Kbits of EEPROM • B uilt-in inadvertent write protection Power-up/power-down protection circuit ry —Protect 0, 1/4, 1/2 or all of EEP ROM array with Block Lock™ protection —In circuit programmable ROM mode 2MHz SPI interface modes (0,0 & 1,1) • Minimize EEPROM programming time 32-byte page write mode —Self-timed write cycle —5ms write cycle time (ty pical) • 2.7V to 5.5V and 4.5V to 5.5V power supply operation • Available packages —8-lead PDIP, 14-lead SOIC .
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