X68257 Micro-Peripheral Datasheet

X68257 Datasheet, PDF, Equivalent


Part Number

X68257

Description

E2 Micro-Peripheral

Manufacture

Xicor

Total Page 14 Pages
Datasheet
Download X68257 Datasheet


X68257
6X86X8X25M7icrocontroller Family Compatible
256K
X68257
32,768 x 8 Bit
E2 Micro-Peripheral
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
DESCRIPTION
The X68257 is an 32K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FUNCTIONAL DIAGRAM
CE, CE
R/W
E
SEL
A8–A14
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
SOFTWARE
DATA
PROTECT
32K x 8
E2PROM
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
6539 ILL F02.2
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
6539-1.7 9/16/96 T0/C1/D2 SH
1
Characteristics subject to change without notice

X68257
X68257
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/W, SEL, and
CE.
Addresses (A8–A14)
High order addresses flow into the device when AS = VIH
and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
Chip Enable (CE)
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (SEL)
When the X68257 is to be used in a 68XX-based
system, SEL is tied to VSS.
Read/Write (R/W)
When the X68257 is to be used in a 68XX-based
system, R/W is tied directly to the microcontroller’s R/W
output.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
PIN NAMES
Symbol
AS
A/D0–A/D7
A8–A14
E
R/W
CE, CE
SEL
VSS
VCC
NC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Device Select—Connect to VSS
Ground
Supply Voltage
No Connect
6539 PGM T01.2
PIN CONFIGURATION
A14
A12
AS
SEL
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
PDIP
SOIC
1 28
2 27
3 26
4 25
5 24
6 23
7 X68257 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
PLCC
VCC
R/W
A13
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6539 FHD F01.3
SEL
CE
NC
NC
NC
NC
NC
NC
A/D0
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 X68257
10
25
24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
A11
NC
E
A10
CE
A/D7
A/D6
6539 FHD F01A.5
2


Features X68257 68XX Microcontroller Family Compa tible 256K X68257 E2 Micro-Peripheral DESCRIPTION 32,768 x 8 Bit FEATURES Multiplexed Address/Data Bus —Dire ct Interface to Popular 68HC11 Family High Performance CMOS —Fast Access Time, 120ns —Low Power —60mA Activ e Maximum —500µA Standby Maximum • Software Data Protection • Toggle Bi t Polling —Early End of Write Detecti on • Page Mode Write —Allows up to 128 Bytes to be Written in One Write Cy cle • High Reliability —Endurance: 10,000 Write Cycle —Data Retention: 1 00 Years • 28-Lead PDIP Package • 2 8-Lead SOIC Package • 32-Lead PLCC Pa ckage The X68257 is an 32K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X682 57 features a multiplexed address and d ata bus allowing direct interface to a variety of popular single-chip microcon trollers operating in expanded multiple xed mode without the need for additiona l interface circuitry. FUNCTIONAL DIAGRAM CE, CE R/W E SEL A8–A14 CONTROL LOGIC X D E C O D E SOFT.
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