E2 Memory. X68C75 Datasheet

X68C75 Datasheet PDF, Equivalent


Part Number

X68C75

Description

Port Expander and E2 Memory

Manufacture

Xicor

Total Page 26 Pages
PDF Download
Download X68C75 Datasheet PDF


X68C75 Datasheet
APPLICATION NOTES
AVA I L A B L E
X68C7AN562S• ALNI6C4 •®ANE662 • AN74
SLIC X68C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between
Planes
• Allows Continuous Execution Of Code
From One Plane While Writing In The
Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X68C75 is a highly integrated peripheral for the
68HC11 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
2 bidirectional 8-bit ports, 16 general purpose registers,
programmable internal address decoding and a multi-
plexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-byte
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
which allows individual blocks of the memory to be
configured as read-only or read/write.
PIN CONFIGURATIONS
DIP
RESET
A12
WC
SEL
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
X68C75
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
R/W
AS
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
E
A10
CE
A/D7
A/D6
A/D5
2899 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2899-2.1 4/11/97 T0/C0/D1 SH
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X68C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2899 ILL F02.3
Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice

X68C75 Datasheet
X68C75 SLIC® E2
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X68C75 is accomplished through the
multiplexed address/data bus of the 68HC11 type con-
trollers. An internal programmable address decoder
maps the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X68C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X68C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 68HC11 microcontroller. The
reading of data from the chip is controlled by the
R/W and E clock signals.
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
the falling edge of AS latches the address present on the
FUNCTIONAL DIAGRAM
address bus into the X68C75, and the falling edge of E
clock latches the data to be written.
The nonvolatile memory of the X68C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X68C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X68C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the nonvolatile memory array to be
treated as 8 independent sections of 1K-bytes. Each of
these sections can be independently enabled for write
operations. This allows segmentation of the memory
contents into writable and non-writable sections, thereby,
allowing certain sections of the device to be secured so
that updates can only occur in a controlled environ-
ment. (e.g. in an automotive application, only at an
authorized service center). The Block Protect configu-
ration is stored in a nonvolatile register, ensuring that
the configuration data will be maintained after the
device is powered-down.
A0–A15
ADDRESS
LATCH
I/O0–I/O7
I/O
BUFFER
&
LATCH
CE
R/W
E
AS
SEL
WC
RESET
IRQ
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
DATA I/O BUS
RIGHT PLANE
DECODE
16 X 8
GENERAL
PURPOSE
REGISTERS
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
PORT
A
PORT
B
PORT SELECT
SDP
DECODE
MEM. MAP
CONFIG
REGISTER
PORT
SPECIAL
FUNCTION
REGISTERS
2899 ILL F03
2


Features Datasheet pdf APPLICATION NOTES A V A I L A B L E AN62 • AN64 • X68C75 SLIC®AN66 E2 • AN74 SLIC X68C75 SLIC® E2 Microperip heral Port Expander and E2 Memory • H igh Performance CMOS —Fast Access Tim e, 120ns —Low Power • 60mA Active 100µA Standby • PDIP, PLCC, and T QFP Packaging Available DESCRIPTION The X68C75 is a highly integrated peripher al for the 68HC11 family of microcontro llers. The device integrates 8K-bytes o f 5V byte-alterable nonvolatile memory, 2 bidirectional 8-bit ports, 16 genera l purpose registers, programmable inter nal address decoding and a multiplexed address and data bus. The 5V byte-alter able nonvolatile memory can be used as program storage, data storage, or a com bination of both. The memory array is s eparated into two 4K-byte sections whic h allows read accesses to one section w hile a write operation is taking place in the other section. The nonvolatile m emory also features Software Data Prote ction to protect the contents during power transitions, and an advanced Block Protec.
Keywords X68C75, datasheet, pdf, Xicor, Port, Expander, and, E2, Memory, 68C75, 8C75, C75, X68C7, X68C, X68, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)