X76F128 SerialFlash Datasheet
|Total Page||17 Pages|
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
• 16384 Byte+64 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 64 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
The X76F128 is a Password Access Security Supervisor,
containing one 131072-bit Secure SerialFlash array and
one 512-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F128 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F128 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
The X76F128 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7052 10/7/97 T0/C0/D0 SH
7052 FM 01
Characteristics subject to change without notice
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F128 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F128 will be in
standby mode. CS low enables the X76F128, placing it in
the active mode.
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F128 will output 32 bits of ﬁxed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
There are two primary modes of operation for the
X76F128; Protected READ and protected WRITE.
Protected operations must be performed with one of four
The basic method of communication for the device is
established by ﬁrst enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
If the X76F128 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
The basic sequence is illustrated in Figure 1.
CS Chip Select Input
Serial Data Input/Output
SCL Serial Clock Input
Vcc Supply Voltage
NC No Connect
7052 FM T01
7052 FM 02
After each transaction is completed, the X76F128 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
|Features||128K X76F128 Secure SerialFlash DESCRIP TION 16Kx8+64x8 FEATURES • 64-bit P assword Security —Five 64-bit Passwor ds for Read, Program and Reset • 1638 4 Byte+64 Byte Password Protected Array s —Seperate Read Passwords —Seperat e Write Passwords —Reset Password • Programmable Passwords • Retry Count er Register —Allows 8 tries before cl earing of both arrays —Password Prote cted Reset • 32-bit Response to Reset (RST Input) • 64 byte Sector Program • 400kHz Clock Rate • 2 wire Seria l Interface • Low Power CMOS —2.7 t o 5.5V operation —Standby current Les s than 1µ A —Active current less tha n 3 mA • High Reliability Endurance: —100,000 Write Cycles • Data Retent ion: 100 years • Available in: —Sma rtCard Module —TQFP Package The X76F 128 is a Password Access Security Super visor, containing one 131072-bit Secure SerialFlash array and one 512-bit Secu re SerialFlash array. Access to each me mory array is controlled by two 64-bit passwords. These passwords protect read and write operations of the memor.|
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