X84041 E2PROM Datasheet

X84041 Datasheet, PDF, Equivalent


Part Number

X84041

Description

Micro Port Saver E2PROM

Manufacture

Xicor

Total Page 13 Pages
Datasheet
Download X84041 Datasheet


X84041
APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVA I L A B L E
X84041AN10 • AN17 • AN57 • XK84
4K X84041
Micro Port Saver E2PROM
MPSE2PROM
FEATURES
• Direct Interface to Micros
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• 3.3Mbps data transfer rate
• Low Power CMOS
—2.7V to 5.5V Operation
—Standby Current Less than 50µA
—Active Current Less than 1mA
• 45ns Read Access Time
• 8-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• 8-Lead PDIP, 8-Lead SOIC, and
14-Lead TSSOP Packages
DESCRIPTION
The X84041 Micro Port Saver is a 4096-bit CMOS
E2PROM designed for a direct interface to port limited
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial memo-
ries, such as low cost, low power, low voltage operation,
and small package size, while featuring higher data
transfer rates and reduced interface code requirements—
without the need for a dedicated serial bus. The X84041
is organized as a 512 x 8, but is also suitable in 16-bit or
32-bit environments, due to the bit serial nature of the
interface.
The X84041 directly connects to the processor bus and
communicates over a single data line using a sequence
of standard bus read and write operations. This elimi-
nates the need for dedicated port pins, parallel to serial
converters, complicated ASIC implementations, or other
glue logic, lowering system cost.
PIN CONFIGURATION
CE
I/O
WP
VSS
DIP/SOIC
18
27
X84041
36
45
VCC
NC
OE
WE
2704 ILL F01.2
BLOCK DIAGRAM
WP
H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
OE DECODE
AND
WE CONTROL
I/O LOGIC
X
DEC
EEPROM
ARRAY
512 x 8
TSSOP
CE 1
I/O 2
14 VCC
13 NC
NC 3
12 NC
NC 4 X84041 11 NC
NC 5
10 NC
WP 6
9 OE
VSS
7
8 WE
2704 ILL F02a.1
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
2704-4.4 6/12/96 T3/C1/D0 NS
PIN NAMES
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
Y DECODE
DATA REGISTER
2704 ILL F02
2704 PGM T01
1 Characteristics subject to change without notice

X84041
X84041
A Write Protect (WP) pin provides hardware protection
against inadvertent writes to the memory.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
X84041 is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the X84041 on the
I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the X84041.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the X84041 through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the X84041 are disabled. When WP is HIGH, all
functions, including nonvolatile writes, operate normally.
If a nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
The X84041 is a serial 512 x 8 bit E2PROM designed to
interface directly with most microprocessor buses. Stan-
dard CE, OE, and WE signals control the read and write
operations, and a single l/O line is used to send and
receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
the l/O line is active whenever both OE and CE are LOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle be-
tween the write cycles. The address is sent serially, most
significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks on
the bus whenever the X84041 CE pin is HIGH. Once the
16 address bits are sent, a byte of data can be read on
the I/O line by issuing 8 separate read cycles (OE and
CE LOW, WE HIGH). At this point, issuing a reset
sequence will terminate the read sequence, otherwise
the X84041 will await further reads in the sequential
read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address is reached ($1FF), the ad-
dress counter rolls over to address $000 and reading
may be continued indefinitely.
Reset Sequence
The reset sequence resets the X84041 and sets an
internal write enable latch. A reset sequence can be sent
at any time by performing a read/write “0”/read se-
quence (see Figs. 1 and 2). This sequence breaks the
multiple read or write cycle sequences that are normally
used when reading from or writing to the part. This
sequence can be used at any time to interrupt or end a
sequential read or page load. As soon as the write “0”
cycle is complete, the part is reset (unless a nonvolatile
write cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a HIGH
on the l/O pin until a valid read sequence is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the X84041
initiates these operations properly.
2


Features APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E X84041 4K AN10 • AN17 • AN57 • XK84 X84041 Micro P ort Saver E2PROM MPS™ E2PROM FEATUR ES • Direct Interface to Micros —El iminates I/O port requirements —No in terface glue logic required —Eliminat es need for parallel to serial converte rs • 3.3Mbps data transfer rate • L ow Power CMOS —2.7V to 5.5V Operation —Standby Current Less than 50µA — Active Current Less than 1mA • 45ns R ead Access Time • 8-Byte Page Write M ode • Typical Nonvolatile Write Cycle Time: 5ms • High Reliability —100, 000 Endurance Cycles —Guaranteed Data Retention: 100 Years • 8-Lead PDIP, 8-Lead SOIC, and 14-Lead TSSOP Packages DESCRIPTION The X84041 Micro Port Sav er is a 4096-bit CMOS E2PROM designed f or a direct interface to port limited m icrocontroller or I/O limited microproc essor designs. The X84041 provides all of the benefits of serial memories, suc h as low cost, low power, low voltage operation, and small package size, while featuring higher data tra.
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