VPX3225D

PRELIMINARY DATA SHEET MICRONAS VPX 3225D, VPX 3224D Video Pixel Decoders Edition Nov. 9, 1998 6251-432-2PD MICRONAS VPX 3225D, VPX 3224D Contents Page 6 7 8 8 8 8 8 8 8 8 10 10 10 11 11 11 11 11 12 13 13 14 15 16 16 16 16 17 17 17 18 20 20 20 20 21 21 22 23 23 23 23 25 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6. 2.2.7. 2.2.8. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2. 2.6.1.3. 2.6.2. 2.6.3. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. Title Introduction System Architecture Functional Description Analog Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters ADC Range Digitally Controlled Clock Oscillator Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation PAL Compensation/1-H Comb Filter Luminance Notch Filter Video Sync Processing Macrovision Detection (version D4 only) Component Processing Horizontal Resizer Skew Correction Peaking and Coring YCbCr Color Space Video Adjustments Video Output Interface Output Formats YUV 4:2:2 with Separate Syncs/ITU-R601 Embedded Reference Headers/ITU-R656 Embedded Timing Codes (BStream) Bus Shuffler Output Multiplexer Output Ports Video Data Transfer Single and Double Clock Mode Half Clock Mode Video Reference Signals HREF VREF Odd/Even Information (FIELD) VACT PRELIMINARY DATA SHEET 2 Micronas PRELIMINARY DATA SHE...