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V320 Dataheets PDF



Part Number V320
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description V320 8-Bit Registered Bus Transceiver
Datasheet V320 DatasheetV320 Datasheet (PDF)

V320 8-Bit Registered Bus Transceiver April 1998 Revised October 1998 V320 8-Bit Registered Bus Transceiver General Description The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels (VIH/VIL) for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-f.

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V320 8-Bit Registered Bus Transceiver April 1998 Revised October 1998 V320 8-Bit Registered Bus Transceiver General Description The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels (VIH/VIL) for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode (OE HIGH) A data may be stored in the B register and/or B data may be stored in the A register. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s Guaranteed output skew s Guaranteed MOS (Multiple Output Switching) Specifications s Output switching specified for both 50 pF and 250 pF, and 500 pF loads s Guaranteed simultaneous switching noise level (VOLP/ VOLV) and dynamic threshold performance (VIHD/VILD) s Glitch free power up/down high impedance for live insertion s BiCMOS technology for high drive and low power dissipation s −40°C to 85°C commercial temperature and VCC specifications s Modified specifications across VCC and temperature (VCC = 5.0V ±1%, T = 25°C ± 20°C) present more realistic system conditions s Available in TSSOP (MTC) Ordering Code: Order Number V320MTC Package Number MTC24 Package Description 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names D OE CLKAB/SELAB CLKBA/SELBA A0–7 B0–7 Description Direction A-to-B (High) B-to A (Low) Output Enable (Active LOW) A-to-B Clock/Select B-to-A Clock/Select A Inputs/Outputs (TTL) B Inputs/Outputs (TTL) © 1998 Fairchild Semiconductor Corporation DS500149.prf www.fairchildsemi.com V320 Functional Table OE H H H L L L L L L L L D X X X H H H H L L L L SELAB SELBA CLKAB CLKBA X X X L L H H X X X X X X X X X X X L L H H H or L LH X X LH H or L LH X X X X H or L X LH X X X X X LH H or L LH Output Input Input Input Input A0–A7 B0–B7 Isolation CLK A Data into A CLK B Data into A Reg. A to B – Transparent CLK A Data into A Reg. Output A Reg. to B (Storage) CLK A Data into A Reg. and B output B to A – Transparent CLK B Data into B Reg. B Reg. to A (Storage) CLK B Data into B Reg.and A output Function L = Low H = High LH = Low to High transition X = Don’t Care Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 V320 Absolute Maximum Ratings(Note 1) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into A-port/B-port IOL DC Output Source Current from A-port/B-port IOH DC Input Diode Current (IIK) VI < 0 V ESD Rating typical Storage temperature (TSTG) Max IOL (Current Applied to a LOW Output) −30 mA to +5.0 mA > 2000V −65° C to +15°C 2 X IOL Spec. −0.5V to +7.0V −0.5V to VCC +0.5V 64 mA −32 mA −0.5V to +7.0V Recommended Operating Conditions Supply Voltage VCC Operating VCC Minimum Input Edge Rate Data Input Enable Clock Operating Temperature (TA) 50 mV/ns 20 mV/ns 100 mV/ns −40°C to +85°C 4.5V to 5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics (4.5V < VCC ≤ 5.5V) Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) VCC Symbol Parameter Min Typ (V) VIH B-Port/A-Port HIGH Level Input Voltage 4.5–5.5 4.95–5.05 VIL B-Port/A-Port LOW Level Input Voltage 4.5–5.5 4.95–5.05 VOH IOH VOL IOL IOS IOFF ICCH ICCI ICCZ B-Port/A-Port HIGH Level Output Voltage B-Port/A-Port High Level Output Current Drive B-Port/A-Port LOW Level Output Voltage B-Port/A-Port Low Level Output Current Drive (Sink) B-Port/A-Port Short Circuit Current A-Port and Control Pins Power-OFF Leakage Current 4.5 4.5 4.5 4.5 4.5 5.5 0.0 5.5 5.5 5.5 2.5 2.0 −32 0.55 64 −100 −275 100uA 250 30 50 mA V mA mA uA uA mA uA 2.0 1.8 (Note 3) 0.8 1.2 (Note 3) V −3 mA −32 mA VOH = 2.0V 64 mA VOL = 0.55V VOUT = 0.0V VOUT = .


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