V53C516405A

MOSEL VITELIC V53C516405A 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C516405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60, 70 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +5 V ±10% Power Supply s TTL Interface Description The V53C516405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory. The V53C516405A offers Page mode operation with Extended Data Output. The V53C516405A has a symmetric address, 12-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 4 bits, within a page, with cycle times as short as 20ns. These features make the V53C516405A ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline K Access Time (ns) 50 Power Std. T 60 Temperature Mark Blank V53C516405A Rev. 1.1 March 1998 1 MOSEL VITELIC 24/26 Pin Plastic SOJ /TSOP-II PIN CONFIGURATION Top View VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC ...