V54C316162

MOSEL VITELIC V54C316162V 200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 V54C316162V Clock Frequency (tCK) Latency Cycle Time (tCK) Access Time (tAC ) -5 200 3 5 5 -55 183 3 5.5 5.3 -6 166 3 6 5.5 -7 143 3 7 5.5 Unit MHz clocks ns ns Features s JEDEC Standard 3.3V Power Supply s The V54C316162V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave s UDQM & LDQM for byte masking s Auto & Self Refresh s 4K Refresh Cycles/64 ms s Burst Read with Single Write Operation Description The V54C316162V is a 16,777,216 bits synchronous high data rate DRAM organized as 2 x 524,288 words by 16 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation. V54C316162V Rev.2.9 September 2001 1 MOSEL VITELIC 50 Pin Plastic TSOP-II PIN CONFIGURATION Top View Pin Names CLK CKE CS Clock Input Clock Enable Chip Select V54C316162V VCC I/O1 I/O2 VSSQ I/O3 I/O4 VCCQ I/O5 I/O6 VSSQ I/O7 I/O8 VCCQ LDQM...