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V55C2128164VB Dataheets PDF



Part Number V55C2128164VB
Manufacturers Mosel Vitelic Corp
Logo Mosel Vitelic  Corp
Description 128Mbit LOW-POWER SDRAM 2.5 VOLT/ TSOP II / BGA PACKAGE 8M X 16
Datasheet V55C2128164VB DatasheetV55C2128164VB Datasheet (PDF)

MOSEL VITELIC V55C2128164V(T/B) 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 PRELIMINARY 6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2 Clock Access Time (tAC1) CAS Latency = 1 166 MHz 6 ns 5.4 ns 5.4 ns 19 ns 7PC 143 MHz 7 ns 5.4 ns 5.4 ns 19 ns 7 143 MHz 7 ns 5.4 ns 6 ns 19 ns 8PC 125 MHz 8 ns 6 ns 6 ns 19 ns 10 100MHz 10 ns 7 ns 8 ns 22 ns Features ■ 4 banks x 2Mbit x 16 organization.

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MOSEL VITELIC V55C2128164V(T/B) 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 PRELIMINARY 6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2 Clock Access Time (tAC1) CAS Latency = 1 166 MHz 6 ns 5.4 ns 5.4 ns 19 ns 7PC 143 MHz 7 ns 5.4 ns 5.4 ns 19 ns 7 143 MHz 7 ns 5.4 ns 6 ns 19 ns 8PC 125 MHz 8 ns 6 ns 6 ns 19 ns 10 100MHz 10 ns 7 ns 8 ns 22 ns Features ■ 4 banks x 2Mbit x 16 organization ■ High speed data transfer rates up to 166 MHz ■ Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge ■ Single Pulsed RAS Interface ■ Data Mask for Read/Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency:1, 2, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 1, 2, 4, 8, Full page for Sequential Type 1, 2, 4, 8 for Interleave Type ■ Multiple Burst Read with Single Write Operation ■ Automatic and Controlled Precharge Command ■ Random Column Address every CLK (1-N Rule) ■ Power Down Mode and Clock Suspend Mode ■ Deep Power Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 4096 cycles/64 ms ■ Available in 54-ball FBGA, with 9x6 ball array with 3 depupulated rows, 9x8 mm and 54 pin TSOP II ■ VDD=2.5V, VDDQ=1.8V ■ ■ Programmable Power Reduction Feature by partial array activation during Self-Refresh ■ Operating Temperature Range Commercial (0°C to 70°C) Extended (-25°C to +85°C) Device Usage Chart Operating Temperature Range 0°C to 70°C -25°C to 85°C Package Outline T/B • • Access Time (ns) 6 • • 7PC • • 7 • • 8PC • • 10 • • Temperature Mark Commercial Extended V55C2128164V(T/B) Rev. 1.2 August 2002 1 MOSEL VITELIC V55C2128164V(T/B) V 55 C 2 12816 Mosel Vitelic Manufactured Low Power Synchronous DRAM Device Number 4 S X B Speed 6 ns 7 ns 8 ns 10 nsComponent Package Component Rev Level A = 0.14um Description BGA Pkg. B Pin Count 54 C=CMOS Family 2.5V Supply Voltage 128Mb(4K Refresh) 4 Banks S=SSTL 60 Pin WBGA PIN CONFIGURATION Top View Pin Configuration for x16 devices: 1 2 3 A B C D E F G H J 7 8 9 VDD DQ1 DQ3 DQ5 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS CKE A9 A6 A4 VDDQ DQ0 VSSQ DQ2 VDDQ DQ4 VSSQ DQ6 VDD LDQM DQ7 CAS BA0 A0 A3 RAS BA1 A1 A2 WE CS A10 VDD UDQM CLK NC A8 VSS A11 A7 A5 < Top-view > V55C2128164V(T/B) Rev.1.2 August 2002 2 MOSEL VITELIC V55C2128164V(T/B) V 55 C 2 12816 4 S X T Mosel Vitelic Manufactured Low Power Synchronous DRAM Device Number Speed 6 ns 7 ns 8 ns 10 ns Component Package Component Rev Level A = 0.14um Description TSOP-II Pkg. T Pin Count 54 C=CMOS Family 2.5V Supply Voltage 8Mx16(4K Refresh) 4 Banks S=STTL 54 Pin Plastic TSOP-II PIN CONFIGURATION Top View VCC I/O1 VCCQ I/O2 I/O3 VSSQ I/O4 I/O5 VCCQ I/O6 I/O7 VSSQ I/O8 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 .


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