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V58C265164S Dataheets PDF



Part Number V58C265164S
Manufacturers Mosel Vitelic Corp
Logo Mosel Vitelic  Corp
Description 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16
Datasheet V58C265164S DatasheetV58C265164S Datasheet (PDF)

MOSEL VITELIC V58C265164S 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 PRELIMINARY 4 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 250 MHz 4 ns 4.8 ns 6 ns 45 225 MHz 4.5 ns 5.4 ns 6.75 ns 5 200 MHz 5 ns 6 ns 7.5 ns 55 183 MHz 5.5 ns 6.6 ns 8.25 ns Features I 4 banks x 1Mbit x 16 organization I High speed data transfer rates with system frequency up to 250 MHz I Data Mask for Write Control (DM) I Four Banks controlled by BA0 & BA1 I Programmable C.

  V58C265164S   V58C265164S



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MOSEL VITELIC V58C265164S 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 PRELIMINARY 4 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 250 MHz 4 ns 4.8 ns 6 ns 45 225 MHz 4.5 ns 5.4 ns 6.75 ns 5 200 MHz 5 ns 6 ns 7.5 ns 55 183 MHz 5.5 ns 6.6 ns 8.25 ns Features I 4 banks x 1Mbit x 16 organization I High speed data transfer rates with system frequency up to 250 MHz I Data Mask for Write Control (DM) I Four Banks controlled by BA0 & BA1 I Programmable CAS Latency: 2, 2.5, 3 I Programmable Wrap Sequence: Sequential or Interleave I Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type I Automatic and Controlled Precharge Command I Suspend Mode and Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: 4096 cycles/64 ms I Available in 66-pin 400 mil TSOP-II I SSTL-2 Compatible I/Os I Double Data Rate (DDR) I Bidirectional Data Strobe (DQs) for input and output data, active on both edges I On-Chip DLL aligns DQ and DQs transitions with CLK transitions I Differential clock inputs CLK and CLK I Power supply 2.5V ± 0.2V Description The V58C265164S is a four bank DDR DRAM organized as 4 banks x 1Mbit x 16. The V58C265164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline JEDEC 66 TSOP II • CLK Cycle Time (ns) -4 • Power -55 • -45 • -5 • Std. • L • Temperature Mark Blank V58C265164S Rev. 1.7 August 2001 1 MOSEL VITELIC 66 Pin Plastic TSOP-II PIN CONFIGURATION Top View VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS V58C265164S Pin Names CLK, CLK CKE CS RAS CAS WE UDQS, LDQS A0–A11 BA0, BA1 DQ0–DQ15 UDM, LDM VDD VSS VDDQ VSSQ NC VREF Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe (Bidirectional) Address Inputs Bank Select Data Input/Output Data Mask Power (+2.5V) Ground Power for I/O’s (+2.5V) Ground for I/O’s Not connected Reference Voltage for Inputs 64M DDR SDRAM V58C265164S Rev. 1.7 August 2001 2 MOSEL VITELIC Capacitance* TA = 0 to 70°C, VCC = 2.5 V ± 0.2 V, f = 1 Mhz Symbol Parameter CI1 CI2 CIO CCLK Input Capacitance (A0 to A11) Input Capacitance RAS, CAS, WE, CS, CKE Output Capacitance (DQ) Input Capacitance (CCLK, CLK) V58C265164S Absolute Maximum Ratings* Max. Unit 5 5 pF pF Operating temperature range .................. 0 to 70 °C Storage temperature range ................-55 to 150 °C Input/output voltage.................. -0.3 to (VCC+0.3) V Power supply voltage .......................... -0.3 to 4.6 V Power dissipation ...........................................1.6 W Data out current (short circuit).......................50 mA *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.5 4 pF pF *Note: Capacitance is sampled and not 100% tested. Block Diagram Column Addresses A0 - A7, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1 Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Memory array Column decoder Sense amplifier & I(O) bus Row decoder Memory array Column decoder Sense amplifier & I(O) bus Row decoder Memory array Bank 2 Row decoder Memory array Bank 3 Bank 0 Bank 1 4096 x 256 x 16 bit 4096 x 256 x 16 bit Column decoder Sense amplifier & I(O) bus 4096 x 256 x 16 bit Column decoder Sense amplifier & I(O) bus 4096 x 256 x 16 bit Input buffer Output buffer Control logic & timing generator I/Q0-IQ15 CKE RAS CAS WE CS CLK, CLK DLL Strobe Gen. Data Strobe UDM LDM CLK CLK DQS V58C265164S Rev. 1.7 August 2001 3 MOSEL VITELIC Signal Pin Description Pin CLK CLK CKE V58C265164S Type Input Signal Pulse Polarity Positive Edge Function The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CLK. Input Level Active High Activates the CLK signal when high and deactivates the CLK .


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