V58C265404S

MOSEL VITELIC V58C265404S HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 PRELIMINARY 6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 166 MHz 6 ns 6.5 ns 7ns 7 143 MHz 7 ns 7.5 ns 8ns 8 125 MHz 8 ns 9 ns 10ns Features s 4 banks x 4Mbit x 4 organization s High speed data transfer rates with system frequency up to 166 MHz s Data Mask for Write Control (DM) s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 2, 2.5, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type s Automatic and Controlled Precharge Command s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 66-pin 400 mil TSOP-II s SSTL-2 Compatible I/Os s Double Data Rate (DDR) s Bidirectional Data Strobe (DQs) for input and output data, active on both edges s On-Chip DLL aligns DQ and DQs transitions with CLK transitions s Differential clock inputs CLK and CLK s Power supply 2.5V ± 0.2V Description The V58C265404S is a four bank DDR DRAM organized as 4 banks x 4Mbit x 4. The V58C265404S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible ...