V58C365164S

MOSEL VITELIC V58C365164S 64 Mbit DDR SDRAM 4M X 16, 3.3VOLT PRELIMINARY 36 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 275 MHz 3.6 ns 4.3ns 5.4ns 4 250 MHz 4 ns 4.8 ns 6 ns 5 200 MHz 5 ns 6 ns 7.5 ns Features ■ 4 banks x 1Mbit x 16 organization ■ High speed data transfer rates with system frequency up to 275 MHz ■ Data Mask for Write Control (DM) ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2, 2.5, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type ■ Automatic and Controlled Precharge Command ■ Suspend Mode and Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 4096 cycles/64 ms ■ Available in 66-pin 400 mil TSOP-II ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQs) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CLK transitions ■ Differential clock inputs CLK and CLK ■ Power supply 3.3V ± 0.3V ■ VDDQ (I/O) power supply 2.5 + 0.2V Description The V58C365164S is a four bank DDR DRAM organized as 4 banks x 1Mbit x 16. The V58C365164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transacti...