V61C3181024

MOSEL VITELIC V61C3181024 128K X 8 HIGH SPEED STATIC RAM PRELIMINARY Features s s s s s s s High-speed: 10, 12, 15 ns Fully static operation All inputs and outputs directly TTL compatible Three state outputs Low data retention current (VCC = 2V) Single 3.3V ± 0.3 Power Supply Low CMOS Standby current of 5 mA max s Packages – 32-pin TSOP – 32-pin 300 mil SOJ Description The V61C3181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The V61C3181024 is available in 32-pin SOJ and TSOP. Functional Block Diagram A0 Row Decoder Memory Array VCC GND A8 I/O0 Input Data Circuit I/O7 A9 CE1 CE2 OE WE Column I/O Column Decoder A16 Control Circuit 3181024 01 Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline T R 10 Access Time (ns) 12 15 Temperature Mark Blank V61C3181024 Rev. 1.3 February 1999 1 MOSEL VITELIC Pin Descriptions A0–A16 Address Inputs These 17 address inputs select one of the 128K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. Output Enable Input OE The Output Enable input is active LOW. When OE...