V61C518256

MOSEL VITELIC V61C518256 32K X 8 HIGH SPEED STATIC RAM Description PRELIMINARY Features s High-speed: 10, 12, 15 ns s Low Power Dissipation: – CMOS Standby: 0.5 mA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 28-pin TSOP (Standard) – 28-pin 300 mil SOJ The V61C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 A1 A6 A10 A13 A14 I/O0 Input Data Circuit I/O7 A2 CE OE WE A5 A11 A12 Row Decoder 512 x 512 Memory Array VCC GND Column I/O Column Decoder Control Circuit 518256-01 Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline T N R 10 Access Time (ns) 12 15 Temperature Mark Blank V61C518256 Rev. 0.3 July 1998 1 MOSEL VITELIC Pin Descriptions A0–A14 Address Inputs These 15 address inputs select one of the 32,768 x 8 bit segments in the RAM. CE Chip Enable Inputs CE is an active LOW input. Chip Enable must be LOW when reading from or writing to the device. When HIGH, the device is in standby mode with I/O pins in the high impedance state. OE Output Enable Input The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the ...