V62C1804096

MOSEL VITELIC Features s s s s s s s s V62C1804096 512K X 8, CMOS STATIC RAM PRELIMINARY Description The V62C1804096 is a very low power CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O’s. This device has an a u to m a tic p o w e r -d o w n mo d e f e a tu r e w h e n deselected. High-speed: 85, 100 ns Ultra low standby current of 2µA (max.) Fully static operation All inputs and outputs directly compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V–2.3V Packages – 36-Ball CSP BGA (8mm x 10mm) Functional Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Input Buffer Row Decoder Sense Amp I/O8 1024 x 4096 I/O1 Column Decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 Control Circuit OE WE CE1 CE2 Device Usage Chart Operating Temperature Range 0°C to 70 °C –40°C to +85°C Package Outline B Access Time (ns) 85 100 L Power LL Temperature Mark Blank I V62C1804096 Rev. 1.0 October 2001 1 MOSEL VITELIC Pin Descriptions A 0–A18 Address Inputs These 19 address inputs select one of the 512K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when...