V62C2164096

MOSEL VITELIC Features s s s s s s s s V62C2164096 256K x 16, 0.17 µm CMOS STATIC RAM PRELIMINARY Description The V62C2164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. High-speed: 70, 85 ns Ultra low CMOS standby current of 4µA (max.) Fully static operation All inputs and outputs directly TTL compatible Three state outputs Ultra low data retention current (VCC = 1.2V) Operating voltage: 2.3V – 3.0V Packages – 44-pin TSOP (Standard) – 48-Ball CSP BGA (8mm x 10mm) Functional Block Diagram A0 A6 A7 A8 A9 I/O1 Input Data Circuit I/O16 A10 UBE LBE OE WE CE1 CE2 A17 Row Decoder 1024 x 4096 Memory Array VCC GND Column I/O Column Decoder Control Circuit Device Usage Chart Operating Temperature Range 0°C to 70°C –40°C to +85°C Package Outline T B Access Time (ns) 70 85 L Power LL Temperature Mark Blank I V62C2164096 Rev. 1.0 November 2001 1 MOSEL VITELIC Pin Descriptions A 0–A17 Address Inputs These 18 address inputs select one of the 256K x 16 bit segments in the RAM. CE1, CE2* Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The ou...