V62C2801024L

V62C2801024L(L) Ultra Low Power 128K x 8 CMOS SRAM Features Ultra Low-power consumption - Active: 25mA at 70ns - Stand-by: 5 µA (CMOS input/output) 1 µA CMOS input/output, L version Single +2.2V to 2.7V Power Supply Equal access and cycle time 70/85/100/150 ns access time Easy memory expansion with CE1, CE2 and OE inputs 1.0V data retention mode TTL compatible, Tri-state input/output Automatic power-down when deselected Functional Description TheV62C2801024L is a low power CMOS Static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE, and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1 ) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. TheV62C2801024LL comes with a 1V data retention feature and Lower Standby Power. The V62C2801024L is available in a 32pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages. Logic Block Diagram 32-Pin TSOP1 / STSOP / 48-fpBGA (See nest page) A11 A9 A8 A13 WE CE2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 C...