V62C518256

MOSEL VITELIC V62C518256 32K X 8 STATIC RAM PRELIMINARY Features s High-speed: 35, 70 ns s Ultra low DC operating current of 5mA (max.) s Low Power Dissipation: – TTL Standby: 3 mA (Max.) – CMOS Standby: 20 µA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 28-pin TSOP (Standard) – 28-pin 600 mil PDIP – 28-pin 330 mil SOP (450 mil pin-to-pin) Description The V62C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 Row Decoder 512 x 512 Memory Array VCC GND A8 I/O0 Input Data Circuit I/O7 A9 CE OE WE Column I/O Column Decoder A14 Control Circuit 518256-01 Device Usage Chart Operating Temperature Range 0°C to 70 °C –40°C to +85°C Package Outline T P F Access Time (ns) 35 70 L Power LL Temperature Mark Blank I V62C518256 Rev. 2.3 November 1998 1 MOSEL VITELIC Pin Descriptions A0–A14 Address Inputs These 15 address inputs select one of the 32,768 x 8 bit segments in the RAM. CE Chip Enable Inputs CE is an active LOW input. Chip Enable must be LOW when reading from or writing to the device. When HIGH, the device is in standby mode with I/O pins in the high imp...