VG36128161BT

VIS Description 16 x 4 (word x bit x bank), respectively. VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII. Features Single 3.3V ( ± 0.3V ) power supply High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2> Fully synchronous operation referenced to clock rising edge Possible to assert random column access in every cycle Quad internal banks controlled by BA0 & BA1 (Bank Select) Byte control by LDQM and UDQM for VG36128161DT Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable /CAS latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh X4, X8, X16 organization LVTTL compatible inputs and outputs 4,096 refresh cycles / 64ms . Document :1G5-0183 Rev.1 Page 1 VIS Pin Configurations VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM VG36128401 (x4) VG36128801 (x8) VG36128161 (x16) VDD NC VDDQ NC DQ0 VSSQ V...