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VG36643241BT-10 Dataheets PDF



Part Number VG36643241BT-10
Manufacturers Vanguard International Semiconductor
Logo Vanguard International Semiconductor
Description CMOS Synchronous Dynamic RAM
Datasheet VG36643241BT-10 DatasheetVG36643241BT-10 Datasheet (PDF)

VIS Description Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package. Features • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle t.

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VIS Description Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package. Features • Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time : 8/10 for LVTTL • High speed clock cycle time : 8/10 for SSTL - 3 • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (Sequential/Interleave) • Automatic precharge and controlled precharge • Auto refresh and self refresh modes • Dual Internal banks controlled by A11 (Bank select) for VG36643211(2) • Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2) • Each Banks can operate simultaneously and independently • LVTTL compatible I/O interface for VG36643211 and VG36643241 • SSTL - 3 compatible I/O interface for VG36643212 and VG36643242 • Random column access in every cycle • x32 organization • Input/Output controlled by DQM0 ~ 3 • 4,096 refresh cycles/64ms • Burst termination by burst stop and precharge command • Burst read/single write option Document : 1G5-0099 Rev.1 Page 1 VIS Pin Configuration VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC A11/BA NC A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC (VREF) NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Pin Description VG36643211 (2) Pin Name A0 - A11 Function Address inputs - Row address A0 - A10 - Column address A0 - A8 A11 : Bank select Data - in/data - out Row address strobe Column address strobe Write enable Ground Power ( + 3.3V) Pin Name DQM0 ~ 3 Function DQ Mask enable DQ0 ~ DQ31 RAS CAS WE VSS VDD CLK CKE CS VDDQ VSSQ (VREF) Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ Reference Voltage, SSTL - 3 only Document : 1G5-0099 Rev.1 Page 2 VIS Pin Configuration VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC A12/BA0 A11/BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC (VREF) NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Pin Description VG36643241 (2) Pin Name A0 - A12 Function Address inputs - Row address A0 - A10 - Column address A0 - A7 A11 & A12 : Bank select Data - in/data - out Row address strobe Column address strobe Write enable Ground Power ( + 3.3V) Pin Name DQM0 ~ 3 Function DQ Mask enable DQ0 ~ DQ31 RAS CAS WE VSS VDD CLK CKE CS VDDQ VSSQ (VREF) Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ Reference Voltage, SSTL - 3 only Document : 1G5-0099 Rev.1 Page 3 VIS Block Diagram CLK CKE Clock Generator Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM Address Mode Register Row Decoder Row Address Buffer & Refresh Counter (Bank D) (Bank C) Bank B Bank A Sense Amplifier Command Decoder CS RAS CAS WE Control Logic Column Address Buffer & Burst Counter Column Decoder & Latch Circuit Input & Output Buffer Latch Circuit DQM Data Control Circuit DQ Note: Bank C and Bank D are for VG36643241(2) only Document : 1G5-0099 Rev.1 Page 4 VIS Absolute Maximum D.C. Ratings Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature Caution Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM Symbol VIN, VOUT VDD, VDDQ IOUT PD TOPT TSTG Value -0.5 to + 4.6 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125 Unit V V mA W °C °C Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification.


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