CMOS Synchronous Dynamic RAM
VIS
Description
Preliminary
VG36648041CT CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM orga...
Description
VIS
Description
Preliminary
VG36648041CT CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
Single 3.3V ( ± 0.3V ) power supply High speed clock cycle time : 7/8ns Fully synchronous with all signals referenced to a positive clock edge Programmable CAS Iatency (2,3) Programmable burst length (1,2,4,8,& Full page) Programmable wrap sequence (Sequential/Interleave) Automatic precharge and controlled precharge Auto refresh and self refresh modes Quad Internal banks controlled by A12 & A13 (Bank select) Each Bank can operate simultaneously and independently LVTTL compatible I/O interface Random column access in every cycle X8 organization Input/Output controlled by DQM 4,096 refresh cycles/64ms Burst termination by burst stop and precharge command Burst read/single write option
The information shown is subject to change without notice. Document : 1G5-0153 Rev.1 Page 1
VIS
Pin Configuration
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD
Preliminary
VG36648041CT CMOS Synchronous Dynamic RAM
VG36648041
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