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UPD75P0076 Dataheets PDF



Part Number UPD75P0076
Manufacturers NEC
Logo NEC
Description 4-BIT SINGLE-CHIP MICROCONTROLLER
Datasheet UPD75P0076 DatasheetUPD75P0076 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µPD75P0076 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the µPD75P0076 supports programming by users, it is suitable for use in prototype testing for system development using the µPD750064, 750066, and 750068 products, and for use in small-lot production. Detailed information about function is provided in the following user’s manual. Be sure to read.

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DATA SHEET MOS INTEGRATED CIRCUIT µPD75P0076 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM capacity. Because the µPD75P0076 supports programming by users, it is suitable for use in prototype testing for system development using the µPD750064, 750066, and 750068 products, and for use in small-lot production. Detailed information about function is provided in the following user’s manual. Be sure to read it before designing: µPD750068 User’s Manual: U10670E FEATURES Compatible with µPD750068 Memory capacity: • PROM : 16384 x 8 bits • RAM : 512 x 4 bits Can operate with same power supply voltage as the mask ROM version µPD750068 VDD = 1.8 to 5.5 V On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V) 8-bit resolution x 8 channels Small shrink SOP package ORDERING INFORMATION Part Number Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) µPD75P0076CU µPD75P0076GT Caution On-chip pull-up resistors by mask option cannot be provided. The information in this document is subject to change without notice. Document No. U10232EJ1V0DS00 (1st edition) Date Published December 1996 N Printed in Japan The mark shows major revised points. © 1995 µPD75P0076 Functional Outline Parameter Instruction execution time Function • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock) • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock) • 122 µs (@ 32.768 kHz with subsystem clock) 16384 x 8 bits 512 x 4 bits • 4-bit operation: 8 x 4 banks • 8-bit operation: 4 x 4 banks 12 Connections of on-chip pull-up resistors can be specified by software: 7 Also used for analog input pins: 4 Connections of on-chip pull-up resistors can be specified by software: 12 Also used for analog input pins: 4 13-V withstand voltage On-chip memory PROM RAM General-purpose register Input/ output port CMOS input CMOS input/output 12 N-ch open-drain input/output pins Total Timer 8 32 4 • • • channels 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) 8-bit basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit • 2-wire serial I/O mode 8-bit resolution x 8 channels (1.8 V ≤ AVREF ≤ VDD) 16 bits • Φ , 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock) • Φ , 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock) • 2, 4, 32 kHz (@ 4.19 MHz with main system clock or @ 32.768 kHz with subsystem clock) • 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock) External: 3, Internal: 4 External: 1, Internal: 1 • Ceramic or crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation STOP/HALT mode T A = –40 to +85 ˚C VDD = 1.8 to 5.5 V • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) • 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch) A/D converter Bit sequential buffer Clock output (PCL) Buzzer output (BUZ) Vectored interrupts Test input System clock oscillator Standby function Operating ambient temperature Power supply voltage Package 2 µPD75P0076 CONTENTS 1. PIN CONFIGURATION (Top View) ................................................................................................... 2. BLOCK DIAGRAM ............................................................................................................................ 3. PIN FUNCTIONS ............................................................................................................................... 3.1 3.2 3.3 3.4 Port Pins ................................................................................................................................................... Non-port Pins ........................................................................................................................................... Equivalent Circuits for Pins .................................................................................................................... 4 5 6 6 7 9 Handling of Unused Pins ......................................................................................................................... 12 4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13 4.1 4.2 Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13 Setting of Stack Bank Selection (SBS) Register .................................................................................... 14 5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068 ........................ 15 6. MEMORY CONFIGURATION ............................................................................................................ 16 7. INSTRUCTION SET ...


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