Document
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD7759
ADPCM SPEECH SYNTHESIZER LSIs
The µ PD7759 is an external ROM type speech synthesis LSI employing the waveform coding method. In addition to the ROM capability of up to 1 Mbit, the µ PD7759 realizes the synthesis of speech sounds of any length by using the ADPCM data transferred from an external ROM. As the synthesizing method, it adopts the ADPCM method and the PCM + waveform element method. The ADPCM method is suitable for synthesizing clear and natural speech sounds, and the PCM + waveform element method is for the synthesis of sound effects and melodies. And by using them together, the
µ PD7759 realizes the long-time synthesis of high-quality sounds.
Because of the short turn-around time of speech analysis, the µ PD7759 can perform the quick system development using a PROM, or the evaluation of an on-chip ROM type of the µ PD7755 family.
FEATURES
5 q Synthesizing method q Sampling frequency q Bit rate (speech) q Number of Messages 5 q External speech data ROM
Parameters Speech data ROM (External) Products Speech (ADPCM) 50 sec. (TYP.) Synthesizing time
Note1
: ADPCM, PCM + waveform element methods used together : 5, 6 or 8 kHz : 20 to 32 K bps : 256 (MAX.)
Melodies & sound effects Note2 (PCM + waveform element) 340 sec. (TYP.)
µ PD7759
1 Mbits
Note 1. The synthesizing time for the speech is the value for a 6 kHz sampling. 2. The synthesizing time for the melodies & sound effects is variable according to their tone.
q Speech output q Host CPU interface q Standby mode q Supply voltage q CMOS technology
: Current sink type analog output, 9-bit D/A converter : Compatible with a 4/8-bit CPU : Pop-noise preventive circuit incorporated : 2.7 to 5.5 V
ORDERING INFORMATION
Part Number Package 40-pin plastic DIP (600 mil) 52-pin plastic QFP ( s 14 mm) Quality grade Standard Standard
µ PD7759C µ PD7759GC-3BH
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-2323A (O.D.No. IC-6960D) Date Published January 1993 Printed in Japan
The mark 5 shows revised points.
©
1988, 1993
µPD7759
PIN CONFIGURATION (Top View)
• 40-pin plastic DIP
ASD5 ASD6 ASD7 I0 I1 I2 I3 I4 I5 I6 I7 AEN/ WR SAA DRQ ALE REF AVO BUSY RESET GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD ASD4 ASD3 ASD2 ASD1 ASD0 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS X2 X1 ST MD
• 52-pin plastic QFP
NC CS X2 X1 ST MD NC GND RESET BUSY AVO REF NC NC A0 A1 A2 A3 A4 NC A5 A6 A7 A8 ASD0 NC 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 25 42 24 43 23 44 22 45 21 46 20 µ PD7759GC-3BH 47 19 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 10 11 12 13
NC ALE DRQ SAA AEN / W R I7 NC I6 I5 I4 I3 I2 NC
BLOCK DIAGRAM
ASD0 to ASD7
A0 to A8
NC ASD1 ASD2 ASD3 ASD4 VDD NC ASD5 ASD6 ASD7 I0 I1 NC
µ PD7759C
SAA ALE DRQ MD BUSY CS ST
X1 ROM Address & Speech Data Interface OSC X2
REF
AEN/ WR System Controller ADPCM Decoder
D/A Converter
AVO
RESET VDD GND Message Select Interface
I0 to I7
2
µPD7759
1. PIN FUNCTIONS
1.1 COMMON FUNCTION TO ALL MODES
Pin (Abbreviation) V DD DRQ 52-pin QFP Pin No. 6 24 40-pin DIP Pin No. 40 14 — Output Power supply (2.7 to 5.5 V) Speech synthesis data request. D/A converter reference current input. The sink-load current input causes the output current of the REF 28 16 Input D/A converter to change. The D/A converter reference current is passed to V DD via a resistor. In standby mode, REF is set to high impedance. Analog speech signal output. AVO outputs a unipolar sink-load current. The output current is reduced to 0 when the µ PD7759 is in the AVO 29 17 Output standby mode. The output current of the D/A converter from AVO is changed according to the input current from REF. Maximum output current of the D/A converter is approx. the 34 times the REF input current. Active-low BUSY signal output. When inputting ST signal, BUSY 30 18 Output it outputs a low level signal. MD, ST and WR are invalid while BUSY is low. In standby mode, BUSY is set to high impedance. Reset input. In standby mode, RESET must be at low level more than 12 RESET 31 19 Input clock cycles after clock oscillation becomes stable. In operation mode, RESET must be at low level for 12 clock cycles (oscillation clock). GND 32 20 — Ground. Ceramic resonator connection for generating a clock signal. The 640 kHz ceramic resonator can be connected. In standby mode, the µ PD7759 outputs a low-level to X1 and X2 37 24 — a high-level to X2. I/O Function
5
X1
36
23
—
1, 7, 13, NC 14, 20, 26, 27, 33, 39, 40, 46, 52 — — No Connection
3
µPD7759
1.2 PIN FUNCTION FOR STAND ALONE MODE
Pin (Abbreviation) I0 I1 I2 I3 I4 I5 I6 I7 52-pin QFP Pin No. 11 12 15 16 17 18 19 21 40-pin DIP Pin No. 4 5 6 7 8 9 10 11 Output/ Input In.